IMD 1.17: 11/11/2014 13:06:40 82VKXBVERDOS B* VERSADOS/RMS68K OBJECT 4.3 SN=39358 11 OF 11  BT1182VKXBVERDOS 0420¾x->>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>•NOTICEš<<<<<<<*‚>>>>>>>µ<<<<<<<>*‚>>>>>>>…When�incorporating�any�drivers�during�SYSGEN„<<<<<<<?*‚>>>>>>>…that�require�memory�allocated�for�them�as�perƒ<<<<<<<?*‚>>>>>>>…the�driver�package�instructions�-�this�is�theƒ<<<<<<<,*‚>>>>>>>…spot�the�file(s)�go�into!!–<<<<<<<*‚>>>>>>>µ<<<<<<<=*‚>>>>>>>…This�is�also�the�spot�for�code�for�a�driver…<<<< <<<>*‚>>>>>>>…that‚requires�other�types�of�initialization,ƒ<<<<<<<0*‚>>>>>>>…such‚as�clearing�an�interrupt.‘<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>‘MERGE�IT�HERE—<<<<<<<*<*ˆWhen�you�write�the�code�that�is�to�be�merged�here,�wrap�it*ˆaround�with�the�following:*:*ˆAt�the�beginning,�with�DRVRxOUT�referring�to�your�unique*ˆlabel,�put�this�code:*'*‹PEA„DRVRxOUT(PC)„IF�BUS�ERROR�OCCURS,*¢RETURN�OR�GO�ON�TO�NEXT*¢DRIVER'S�INITIALIZATION**‹MOVE.W�#'BE',-(A7)…SAVE�'BUS�ERROR'�FLAG*9*ˆThen�insert�the�code�to�do�what�you�need�to�do�for�this*ˆparticular�driver.**ˆAt�the�end,�put�this:***‹LEA„6(A7),A7ˆREMOVE�BUS�ERROR�FROM�STACK*DRVRxOUTƒEQU„**=*ˆIn�this�way,�if�the�code�for�one�driver�causes�a�bus�error,.*ˆthe�code�for�other�drivers�will�be�executed.*E*‚>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<G***********************************************************************‰END éééééé ‰SECTIONƒ8 ŠRTS  ŠENDééééé ééR4VECTTBLƒIDNTƒ5,1�RMS68K�vector�table�for�the�VME110.O*v*****************************************************************************O*******************************************************************************O**********************************************************************************É***?***…ROUTINE:‚VECTTBL�--�RMS68K�VECTOR�TABLE�FOR�THE�VME110.Œ******É***J***…ENVIRONMENT:‚Part�of�the�RMS68K�exec�for�the�Motorola�68000�family.***G***‡Copyright�1983�by�Motorola,�Inc.‚This�version�is�for�the�VME110‚*** ***‡monoboard�microcomputer.ª******É***E***…FUNCTION:‚This�table�gets�linked�with�RMS68K.‚When�the�system…***C***‡boots,�the�exec�initializer�finds�this�table�and�uses�it�to‡***:***‡take�over�vectors�in�the�processor's�vector�table.�******É***O*******************************************************************************O*******************************************************************************O*^***************************************************************************** *,*‚Revision�history�(add�new�changes�to�top).*…Date†Author‚Changes@*…--------‚------‚----------------------------------------------*…10/25/83ƒSJF„Initial�writing.*  *E*‚XREF's.‚Note�that�there�are�many�more�XREF's�created�by�invocations8*‚of�the�VECTOR�macro;�those�XREF's�are�not�listed�here.*.ŠXREFƒCOMINT�Common�interrupt�handler�routine.   **‚Included�files:*5*‰9995.&.STR.EQ�The�section�number�to�use�is�in�here.*ŠNOLISTŠINCLUDE�9995.&.STR.EQŠLISTŠPAGE*E*‚The�VECTOR�macro�defines�entries�in�the�vector�table.‚The�format�is%*‰VECTOR‚,5*‚There�are�two�special�values�for�:,*‰0�=�COMINT�(the�common�interrupt�handler).(*‰1�=�don't�take�over�the�vector�at�all.E*‚Entries�in�the�vector�table�must�be�assigned�in�order--that�is,�theB*‚vector�#'s�in�the�VECTOR�invocations�must�be�in�ascending�order.H*‚In�the�case�where�two�contiguous�VECTOR�invocations�leave�a�gap�in�the[5d<l(K*‚vector�#'s,�those�vector�#'s�in�the�gap�will�be�assigned�the�same�handler9*‚as�that�of�the�lower�vector�#�of�the�pair.‚For�example,+*‰VECTOR�$23,0ŽPoints�$23�to�$27�to�COMINT.-*‰VECTOR�$28,1ŽLeaves�$28�to�$2F�as�they�are.-*‰VECTOR�$30,ROUTINE1‡Points�$30�to�ROUTINE1.G*‚If�the�gap�to�be�filled�has�a�second�parameter�other�than�0�or�1,�theJ*‚address�assigned�to�the�vector�will�be�incremented�by�2�for�each�vector:7*‰VECTOR�$23,XŽPoints�$23�to�X,�$24�to�X+2,�$25�to�X+4.$*‰VECTOR�$26,0ŽPoints�$26�to�COMINT.'*‚The�end�of�the�list�is�signified�by�a*‰DC.Lƒ0F*‚and�the�second�parameter�of�the�last�prior�VECTOR�invocation�will�beK*‚applied�to�all�further�vectors,�up�to�$FF.‚Again,�if�the�second�parameterK*‚was�not�a�0�or�1,�the�address�assigned�to�the�vectors�will�be�incremented#*‚by�2�for�each�vector�in�sequence.* VECTOR„MACROŒIFLEƒ\1-VECT_NUM0ŽFAILƒ499ŒVector�#'s�must�be�in�ascending�order!ŽMEXITŒENDCŒIFNCƒ'\2','0'ŽIFNCƒ'\2','1'�XREFƒ\2ŽENDCŒENDCVECT_NUM„SET„\1 ŒDC.Lƒ\1<<24+\2ŠENDM  * *‚First�set�up�the�table�header.*ŠSECTION�LEVEL00  0ŠDC.Lƒ'!VCT'�Dump�eyecatcher�for�'VeCtor�Table.'2ŠDC.LƒCOMINT�Put�the�address�of�COMINT�here�so�the"*§exec�initializer�can�find�it;�he#*§isn't�linked�with�the�exec,�so�he*§wouldn't�know�otherwise.ŠPAGE*)*‚Here�are�the�actual�vector�assignments.I*‚Notice�that�whether�or�not�the�illegal�instruction�vector�is�taken�overE*‚by�RMS68K�is�controlled�by�an�sysgen�parameter.‚During�RMSGEN,�this$*‚parameter�is�substituted�such�thatA*„0�=�the�exec�should�leave�the�illegal�instruction�vector�alone.?*„1�=�the�exec�should�take�over�the�illegal�instruction�vector.J*‚You�might�want�the�exec�to�leave�the�illegal�instruction�vector�alone�ifI*‚you�want�to�use�the�ROM�debugger,�since�it�uses�illegal�instructions�as*‚breakpoints.* 8VECT_NUM‚SET„1’Initialize�the�vector�number�to�1�so�that&*§the�lowest�vector�number�that�can�be*§set�afterwards�is�2. ŠVECTOR�$02,PROGINT2‡Bus�error.#ŠVECTOR�$03,PROGINT3‡Address�error.$*§If�we're�not�supposed�to�take�over/ŠIFEQƒ\ILLINSTRŠthe�illegal�instruction�vector,9ŠVECTOR�$04,1Žleave�the�illegal�instruction�vector�alone.ŠENDC–*!*§If�we�are�supposed�to�take�over/ŠIFNEƒ\ILLINSTRŠthe�illegal�instruction�vector,>ŠVECTOR�$04,PROGINT4‡take�over�the�illegal�instruction�vector.ŠENDC–*#ŠVECTOR�$05,PROGINT5‡Division�by�0.+*‚in�sequence„$06,PROGINT6ŠCHK�instruction.-*‚in�sequence„$07,PROGINT7ŠTRAPV�instruction./*‚in�sequence„$08,PROGINT8ŠPrivilege�violation.'ŠVECTOR�$09,PROGINT9‡Instruction�trace.8ŠVECTOR�$0A,PROGINTA‡Reserved�instruction�opcodes�$AXXX.>*‚in�sequence„$0B,PROGINTBŠReserved�instruction�opcodes�$FXXX.'ŠVECTOR�$0C,0Ž($0C�-�$17�go�to�COMINT.)'ŠVECTOR�$18,SPURINTˆSpurious�interrupt.)ŠVECTOR�$19,0ŽI/O�channel�IRQ1*�(COMINT).)ŠVECTOR�$1A,0ŽI/O�channel�IRQ2*�(COMINT).)ŠVECTOR�$1B,0ŽI/O�channel�IRQ3*�(COMINT).)ŠVECTOR�$1C,0ŽI/O�channel�IRQ4*�(COMINT).-ŠVECTOR�$1D,0ŽACIA�(6850)�interrupt�(COMINT).)ŠVECTOR�$1E,TIMEINTˆPTM‚(6840)�interrupt.9ŠVECTOR�$1F,1ŽSoftware�abort�and/or�VMEbus�ACFAIL*�and/or(*§VMEbus�SYSFAIL*.‚We�essentially�ignore&*§ACFAIL*�and�SYSFAIL*,�and�leave�this'*§vector�pointing�to�the�bug's�software*§abort�routine.ŠVECTOR�$20,TRAP0ŠTRAP�#0.ŠVECTOR�$21,TRAP1ŠTRAP�#1.#ŠVECTOR�$22,TRPVCT2ˆTRAP�#2�to�#15.'ŠVECTOR�$30,0Ž($30�-�$FF�go�to�COMINT.)  !ŠDC.Lƒ0’(End�of�table�indicator.)   ŠENDééC‚******************************************************************&‚*�Sysgen�command�file�VME110.RMS.CD *C‚******************************************************************‚*‚INCLUDE…C8OC.SYSPAR.CI‚**‰RMS†=�$40000�Address�where�RMS68K�starts.‚*D‚*‚Now�indicate�whether�or�not�the�exec�should�take�over�the�illegalD‚*‚instruction�vector.‚If�you�are�going�to�be�using�the�ROM�debuggerF‚*‚to�set�breakpoints,�then�you'll�want�the�illegal�instruction�vectorC‚*‚left�as�the�debugger�has�it�set.‚In�an�environment�where�the�ROMC‚*‚debugger�will�not�be�used,�you�will�want�RMS68K�to�field�illegal‚*‚instructions�as�exceptions.‚*.‰ILLINSTR�=�1’Illegal�instruction�vector�flag:#‚*¨0�=�RMS�should�not�take�it�over.‚*¨1�=�RMS�should…take�it�over.N‚*****************************************************************************‚**‚*ˆNow�we�generate�the�RMS68K�load�module.‚*N‚*****************************************************************************‚*‚*‚*‚*(‚*‚Now�create�a�VECTTBL� for�this�system.‚*‰SUBS†VME110.VECTTBL.AG:‰ASM‡VME110.VECTTBL.AG,VME110.VECTTBL.RO,VME110.VECTTBL.TF‚*‚*‚Now�link�it�all�together.‚*‰RMS0LO‚=�\RMS‰RMS0HI‚=�\RMS+$FF‰RMS2LO‚=�\RMS+$100‰SUBS†VME110.RMS.LG‚LINKˆVME110.RMS.LG‚=DEL�.&.SYSPAR.RO(‚=COPY‡VME110.VECTTBL.TF,VME110.RMS.LL;A ‚=COPY‡SYSGEN.TF,VME110.RMS.LL;A‚=DELƒ*.*.TF;Y‚*‚END‰ éét.=/*=/*†Important�note:5=/*†The�order�of�the�INPUT�modules�for�this�LINK�must=/*†be�as�specified�below.=/*=LINK ,\LINK2TF,\LINKLS;IXMHRINPUT M68XXX.INIT.ROINPUT VME110.INITIO1.ROEND=ENDééééééé} =/*=/*†Important�note:5=/*†The�order�of�the�INPUT�modules�for�this�LINK�must=/*†be�as�specified�below.=/*=LINK ,INIT,\LINKLS;HAMIXSSEGMENT .INT:8 \INTSTRINPUT \LINK1TFINPUT VME110.INITIO2.ROINPUT M68XXX.INITDAT.ROINPUT C8OC.SYSPAR.ROEND=END éééééé† =/*7=/*†VME110.RMS.LG�--�RMSGEN�link�chain�file�for�RMS68K.=/*=/*2=LINK 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IN†M68XXX.WTEVENT.ROINPUTƒM68XXX.RMSPATCH.ROEND=ENDéééééééO1VECTTBL ASYST'VME110 XVECTTBLAG!ƒRMS68K vector table for the VME110.Š2pPROGINT2 pPROGINT3 pPROGINT4 pPROGINT5 pPROGINT9 pPROGINTA pTIMEINT pSPURINT pTRAP0 pTRAP1 pCOMINT pTRPVCT2 "Xr3?�p!VCT(,,,,, , ,,, ,!,"04éééééé  'VM01 RMS CDµµ4VECTTBL AG¾¾ŽINITIO AG×׃RMS LGðð`INT LG VECTTBL RO  C‚******************************************************************$‚*�Sysgen�command�file�VM01.RMS.CD *C‚******************************************************************‚*‚INCLUDE…C8OC.SYSPAR.CI‚*(‰RMS†=�$E00�Address�where�RMS68K�starts.‚*‚*‚NOTE:;‚*‚There�are�two�versions�of�VM01�board�available.‚The�only?‚*‚difference�is�the�size�of�on-board�RAM.�VM01-1�has�32Kbytes,A‚*‚VM01-2�has�64Kbytes.‚All�VM01�related�files�are�set-up�for�the?‚*‚64K�version.�For�the�32k�version�set�the�above�RMS�parameter9‚*‚to�$10E00.�RMS�must�be�linked�to�run�in�off-board�ram.‚*D‚*‚Now�indicate�whether�or�not�the�exec�should�take�over�the�illegalD‚*‚instruction�vector.‚If�you�are�going�to�be�using�the�ROM�debuggerF‚*‚to�set�breakpoints,�then�you'll�want�the�illegal�instruction�vectorC‚*‚left�as�the�debugger�has�it�set.‚In�an�environment�where�the�ROMC‚*‚debugger�will�not�be�used,�you�will�want�RMS68K�to�field�illegal‚*‚instructions�as�exceptions.‚*.‰ILLINSTR�=�1’Illegal�instruction�vector�flag:#‚*¨0�=�RMS�should�not�take�it�over.‚*¨1�=�RMS�should…take�it�over.N‚*****************************************************************************‚**‚*ˆNow�we�generate�the�RMS68K�load�module.‚*N‚*****************************************************************************‚*‚*‚*‚*(‚*‚Now�create�a�VECTTBL�for�this�system.‚*‰SUBS†VM01.VECTTBL.AG4‰ASM‡VM01.VECTTBL.AG,VM01.VECTTBL.RO,VM01.VECTTBL.TF‚*‚*‚Now�link�it�all�together.‚*‰RMS0LO‚=�\RMS‰RMS0HI‚=�\RMS+$FF‰RMS2LO‚=�\RMS+$100‰SUBS†VM01.RMS.LG‚LINKˆVM01.RMS.LG‚=DEL�.&.SYSPAR.RO$‚=COPY‡VM01.VECTTBL.TF,VM01.RMS.LL;A‚=COPY‡SYSGEN.TF,VM01.RMS.LL;A‚=DELƒ*.*.TF;Y‚*‚END‰ é­52VECTTBLƒIDNTƒ5,1�RMS68K�vector�table�for�the�VM01.O*v*****************************************************************************O*******************************************************************************O**********************************************************************************É***=***…ROUTINE:‚VECTTBL�--�RMS68K�VECTOR�TABLE�FOR�THE�VM01.Ž******É***J***…ENVIRONMENT:‚Part�of�the�RMS68K�exec�for�the�Motorola�68000�family.***E***‡Copyright�1983�by�Motorola,�Inc.‚This�version�is �for�the�VM01„*** ***‡monoboard�microcomputer.ª******É***E***…FUNCTION:‚This�table�gets�linked�with�RMS68K.‚When�the�system…***C***‡boots,�the�exec�initializer�finds�this�table�and�uses�it�to‡***:***‡take�over�vectors�in�the�processor's�vector�table.�******É***O*******************************************************************************O*******************************************************************************O*^***************************************************************************** *,*‚Revision�history�(add�new�changes�to�top).*…Date†Author‰ChangesG*…--------‚-------------‚----------------------------------------------+*…10/25/83‚Dick�Vanderlin�Revision�for�VM01(*…10/�4/83‚Steve�FranckƒInitial�writing.*  *E*‚XREF's.‚Note�that�there�are�many�more�XREF's�created�by�invocations8*‚of�the�VECTOR�macro;�those�XREF's�are�not�listed�here.*.ŠXREFƒCOMINT�Common�interrupt�handler�routine.   **‚Included�files:*5*‰9995.&.STR.EQ�The�section�number�to�use�is�in�here.*ŠNOLISTŠINCLUDE�9995.&.STR.EQŠLISTŠPAGE*E*‚The�VECTOR�macro�defines�entries�in�the�vector�table.‚The�format�is%*‰VECTOR‚,5*‚There�are�two�special�values�for�:,*‰0�=�COMINT�(the�common�interrupt�handler).(*‰1�=�don't�take�over�the�vector�at�all.E*‚Entries�in�the�vector�table�must�be�assigned�in�order--that�is,�theB*‚vector�#'s�in�the�VECTOR�invocations�must�be�in�ascending�order.¶5¿9Ç!H*‚In�the�case�where�two�contiguous�VECTOR�invocations�leave�a�gap�in�theK*‚vector�#'s,�those�vector�#'s�in�the�gap�will�be�assigned�the�same�handler9*‚as�that�of�the�lower�vector�#�of�the�pair.‚For�example,+*‰VECTOR�$23,0ŽPoints�$23�to�$27�to�COMINT.-*‰VECTOR�$28,1ŽLeaves�$28�to�$2F�as�they�are.-*‰VECTOR�$30,ROUTINE1‡Points�$30�to�ROUTINE1.G*‚If�the�gap�to�be�filled�has�a�second�parameter�other�than�0�or�1,�theJ*‚address�assigned�to�the�vector�will�be�incremented�by�2�for�each�vector:7*‰VECTOR�$23,XŽPoints�$23�to�X,�$24�to�X+2,�$25�to�X+4.$*‰VECTOR�$26,0ŽPoints�$26�to�COMINT.'*‚The�end�of�the�list�is�signified�by�a*‰DC.Lƒ0F*‚and�the�second�parameter�of�the�last�prior�VECTOR�invocation�will�beK*‚applied�to�all�further�vectors,�up�to�$FF.‚Again,�if�the�second�parameterK*‚was�not�a�0�or�1,�the�address�assigned�to�the�vectors�will�be�incremented#*‚by�2�for�each�vector�in�sequence.* VECTOR„MACROŒIFLEƒ\1-VECT_NUM0ŽFAILƒ499ŒVector�#'s�must�be�in�ascending�order!ŽMEXITŒENDCŒIFNCƒ'\2','0'ŽIFNCƒ'\2','1'�XREFƒ\2ŽENDCŒENDCVECT_NUM„SET„\1ŒDC.Lƒ\1<<24+\2ŠENDM  * *‚First�set�up�the�table�header.*ŠSECTION�LEVEL00  0ŠDC.Lƒ'!VCT'�Dump�eyecatcher�for�'VeCtor�Table.'2ŠDC.LƒCOMINT�Put�the�address�of�COMINT�here�so�the"*§exec�initializer�can�find�it;�he#*§isn't�linked�with�the�exec,�so�he*§wouldn't�know�otherwise.ŠPAGE*)*‚Here�are�the�actual�vector�assignments.I*‚Notice�that�whether�or�not�the�illegal�instruction�vector�is�taken�overE*‚by�RMS68K�is�controlled�by�an�sysgen�parameter.‚During�RMSGEN,�this$*‚parameter�is�substituted�such�thatA*„0�=�the�exec�should�leave�the�illegal�instruction�vector�alone.?*„1�=�the�exec�should�take�over�the�illegal�instruction�vector.J*‚You�might�want�the�exec�to�leave�the�illegal�instruction�vector�alone�ifI*‚you�want�to�use�the�ROM�debugger,�since�it�uses�illegal�instructions�as*‚breakpoints.* 8VECT_NUM‚SET„1’Initialize�the�vector�number�to�1�so�that&*§the�lowest�vector�number�that�can�be*§set�afterwards�is�2. ŠVECTOR�$02,PROGINT2‡Bus�error.#ŠVECTOR�$03,PROGINT3‡Address�error.$*§If�we're�not�supposed�to�take�over/ŠIFEQƒ\ILLINSTRŠthe�illegal�instruction�vector,9ŠVECTOR�$04,1Žleave�the�il legal�instruction�vector�alone.ŠENDC–*!*§If�we�are�supposed�to�take�over/ŠIFNEƒ\ILLINSTRŠthe�illegal�instruction�vector,>ŠVECTOR�$04,PROGINT4‡take�over�the�illegal�instruction�vector.ŠENDC–*#ŠVECTOR�$05,PROGINT5‡Division�by�0.+*‚in�sequence„$06,PROGINT6ŠCHK�instruction.-*‚in�sequence„$07,PROGINT7ŠTRAPV�instruction./*‚in�sequence„$08,PROGINT8ŠPrivilege�violation.'ŠVECTOR�$09,PROGINT9‡Instruction�trace.8ŠVECTOR�$0A,PROGINTA‡Reserved�instruction�opcodes�$AXXX.>*‚in�sequence„$0B,PROGINTBŠReserved�instruction�opcodes�$FXXX.'ŠVECTOR�$0C,0Ž($0C�-�$17�go�to�COMINT.)'ŠVECTOR�$18,SPURINTˆSpurious�interrupt.'ŠVECTOR�$19,0Ž($19�-�$1B�go�to�COMINT.)*ŠVECTOR�$1C,TIMEINTˆM6840�timer�interrupt.'ŠVECTOR�$1D,0Ž($1D�-�$1E�go�to�COMINT.)8ŠVECTOR�$1F,1ŽSoftware�abort�(leave�it�pointing�to�bug).ŠVECTOR�$20,TRAP0ŠTRAP�#0.ŠVECTOR�$21,TRAP1ŠTRAP�#1.#ŠVECTOR�$22,TRPVCT2ˆTRAP�#2�to�#15.'ŠVECTOR�$30,0Ž($30�-�$8C�go�to�COMINT.)'ŠVECTOR�$95,0Ž($95�-�$FF�go�to�COMINT.)!ŠDC.Lƒ0’(End�of�table�indicator.)ŠENDéé‰INCLUDE�9999.M6840.M6840.EQ ‰SECTIONƒ8‰PAGE*J*‚This�code�is�needed�to�satisfy�INIT,�which�is�board-independent�and�must/*‚call�upon�us�to�do�the�board-dependent�stuff.**„Initialize�the�MMU.*5ŠXDEFƒINITMMUŒIt's�easy�for�us�to�initialize�the�MMU,$INITMMUƒRTS—since�we�don't�have�one. **„Start�the�timer�running.*+ŠXREF.S�CRASHSAV‹These�are�found�in�SYSPAR.ŠXREF.S�EXCSTACKŠXREF.S�PTMADDRŠXREF.S�TIMESLICŠXREF.S�TIMINTVŠXREF.S�TIMINTV4 &ŠXREFƒCLOCKFRQ‹These�are�found�in�IND. ŠXREFƒTIMERAŠXREFƒTIMINTVA ŠXREFƒTIMSLIC 1ŠXDEFƒTIMERSTŒEntry�point�to�START�TIMER�routine.TIMERSTDŠMOVE.L�TIMSLIC(PC),TIMESLIC‚Set�the�sysgen�parameter�which�dictates%*§the�#�of�timer�tics�per�time�slice.'‰MOVE.L�TIMERA(PC),A1‡GET�TIMER�ADDRESS#‰MOVE.L�A1,PTMADDRŠSAVE�IT�FOR�EXEC$‰BEQ.S‚TIMER_EXITŠBRANCH�IF�NO�TIMER)‰PEA„TIMERBE(PC)‰WHERE�TO�GO�ON�BUS�ERROR$‰MOVE.W�#'BE',-(A7)‰SET�BUS�ERR�FLAG3‰MOVE.B�#$01,CR2SR(A1)†ALLOW�WRITE�TO�CONTROL�REG�1&‰MOVE.B�#$01,CR13(A1)‡ALL�TIMERS�RESET$‰MOVE.L�#CLOCKFRQ,D0ˆCLOCK�FREQUENCY‰DIVUƒ#4,D0�DIVIDE�BY�4#‰SUB.W‚#1,D0�CLOCK�INTERRUPTS�AT�-1*‰MOVE.W�TIMINTVA(PC),D1…INTERRUPT�INTERVAL ‰MOVE.W�D1,TIMINTVŠSAVE�FOR�EXEC‰MULUƒ#4,D1�MULTIPLY�BY�4*‰SUB.W‚#1,D1�SUBTRACT�1�-�TIMER�GOES�TO�-1!‰MOVE.W�D1,TIMINTV4‰SAVE�FOR�EXEC‰LSL.W‚#8,D1�PUT�IN�HIGH�BYTE)‰ADD.W‚D1,D0�VALUE�FOR�TIMER�3�(2�HALVES)‰MOVEP‚D0,MSBT3(A1)ˆSET�TIMER�34‰MOVE.W�#256,D0�VALUE�FOR�TIMER�1�(OVERFLOW�COUNTER)‰MOVEP‚D0,MSBT1(A1)ˆSET�TIMER�18‰MOVE.B�#$00,CR2SR(A1)†ALLOW�WRITE�TO�CONTROL�REGISTER�3;‰MOVE.B�#$C6,CR13(A1)‡T3--INTERNAL�CLOCK,INTERRUPT�ENABLED,*£OUTPUT�ENABLED,�8-BIT�MODE8‰MOVE.B�#$01,CR2SR(A1)†ALLOW�WRITE�TO�CONTROL�REGISTER�1;‰MOVE.B�#$00,CR13(A1)‡T1--EXTERNAL�CLOCK,�ENABLE�ALL�TIMERS3‰ADDQ.L�#6,SP�Everything�went�OK;�just�get�that�bus4‰BRA.S‚TIMER_EXITŠerror�junk�off�the�stack�and�exit.*;TIMERBE‚MOVE.L‚#CRASHSAV,PTMADDR‚USE�DUMP�POINTER�FOR�TIMER TIMER_EXIT�RTS–Return�to�INIT.ŠPAGE ‰SECTIONƒ8Ï@Ø<à .***********************************************(*†SUBROUTINE�USED�TO�INITIALIZE�IO�PORTS*;*ˆTHIS�ROUTINE�MUST�BE�MODIFIED�FOR�SYSTEM�BEING�INITIALZED* ‰XDEF„INITIO INITIOƒEQU…**/*…INITIALIZE�SERIAL�PORT�2�(FOR�VERSAMODULE�01)*ŒOR‚IPC�FOR�EXORMACS*+‰PEA„INITIOR(PC)„RETURN�IF�BUS�ERROR�OCCURS)‰MOVE.W�#'BE',-(A7)„SAVE�'BUS�ERROR'�FLAG$‰TST.B‚$F7001FˆREAD�COMMAND�REGISTER+‰MOVE.B�#$4E,$F7001DƒINIT�MODE�REG�1�PORT�2+‰MOVE.B�#$3E,$F7001DƒINIT�MODE�REG�2�PORT�25‰MOVE.B�#$36,$F7001FƒRESET�AND�ENABLE�RECEIVER�PORT�2$‰TST.B…$F70017ƒREAD�COMMAND�REGISTER+‰MOVE.B„#$4E,$F70015ˆINIT�MODE�REG�1�PORT�1+‰MOVE.B„#$3E,$F70015ˆINIT�MODE�REG�2�PORT�15‰MOVE.B„#$36,$F70017‡RESET�AND�ENABLE�RECEIVER�PORT�13‰MOVE.B�#$BF,$F70030ƒENABLE�VM�INTERRUPTS�FOR�PORT2)‰LEA„6(A7),A7‡REMOVE�BUS�ERROR�FROM�STACK INITIOR‚RTS‰PAGEE*‚>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>•NOTICEš<<<<<<<*‚>>>>>>>µ<<<<<<<>*‚>>>>>>>…When�incorporating�any�drivers�during�SYSGEN„<<<<<<<?*‚>>>>>>>…that�require�memory�allocated�for�them�as�perƒ<<<<<<<?*‚>>>>>>>…the�driver�package�instructions�-�this�is�theƒ<<<<<<<,*‚>>>>>>>…spot�the�file(s)�go�into!!–<<<<<<<*‚>>>>>>>µ<<<<<<<=*‚>>>>>>>…This�is�also�the�spot�for�code�for�a�driver…<<<<<<<>*‚>>>>>>>…that‚requires�other�types�of�initialization,ƒ<<<<<<<0*‚>>>>>>>…such‚as�clearing�an�interrupt.‘<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>‘MERGE�IT�HERE—<<<<<<<*<*ˆWhen�you�write�the�code�that�is�to�be�merged�here,�wrap�it*ˆaround�with�the�following:*:*ˆAt�the�beginning,�with�DRVRxOUT�referring�to�your�unique*ˆlabel,�put�this�code:*'*‹PEA„DRVRxOUT(PC)„IF�BUS�ERROR�OCCURS,*¢RETURN�OR�GO�ON�TO�NEXT*¢DRIVER'S�INITIALIZATION**‹MOVE.W�#'BE',-(A7)…SAVE�'BUS�ERROR'�FLAG*9*ˆThen�insert�the�code�to�do�what�you�need�to�do�for�this*ˆparticular�driver.**ˆAt�the�end,�put�this:***‹LEA„6(A7),A7ˆREMOVE�BUS�ERROR�FROM�STACK*DRVRxOUTƒEQU„**=*ˆIn�this�way,�if�the�code�for�one�driver�causes�a�bus�error,.*ˆthe�code�for�other�drivers�will�be�executed.*E*‚>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<G*********************************************************************** ŠRTS‰ENDéééééé =/*5=/*†VM01.RMS.LG�--�RMSGEN�link�chain�file�for�RMS68K.=/*=/*.=LINK ,VM01.RMS.LO,VM01.RMS.LL;H,M,I,X,-U,Z=40SEG�RMS0:0�\RMS0LO,\RMS0HISEG�RMS2:2,3,4,5,6,7,15‚\RMS2LOINPUTƒ&.SYSPAR.ROINPUTƒM68XXX.RMS.ROINPUT…VM01.VECTTBL.ROIN†M68XXX.AKRQST.ROIN†M68XXX.ASQALOC.ROIN†M68XXX.ASQEVENT.ROIN†M68XXX.ASQFREE.ROIN†M68XXX.ASQREAD.ROIN†M68XXX.ASQSTATS.ROIN†M68XXX.ASRINT.ROIN†M68XXX.ATSEM.ROIN†M68XXX.BKG.ROIN†M68XXX.CDIR.ROIN†M68XXX.CISR.ROIN†M68XXX.CKDELAY.ROIN†M68XXX.CKEXPAT.ROIN†M68XXX.CMR.ROIN†M68000.COMINT.ROIN†M68XXX.DCLSHAR.ROIN†M68XXX.DELAY.ROIN†M68XXX.DEMON.ROIN†M68XXX.DERQST.ROIN†M68XXX.DESEM.ROIN†M68000.DISPATCH.ROIN†M68XXX.DSEGX.ROIN†M68XXX.DSERVE.ROIN†M68XXX.DSRVX.ROIN†M68XXX.EQDQ.ROIN†M68XXX.EXABRT.ROIN†M68000.EXCEPT.ROIN†M68XXX.EXMMSK.ROIN†M68XXX.EXMON.ROIN†M68XXX.EXMONVR.ROIN†M68XXX.EXQEVENT.ROIN†M68XXX.EXRQPA.ROIN†M68XXX.FNDGSEG.ROIN†M68XXX.FNDTSEG.ROIN†M68XXX.FNDUSEM.ROIN†M68XXX.GETTCB.ROIN†M68XXX.GTDTIM.ROIN†M68XXX.KILLER.ROIN‡NOMMU.LOADMMU.ROIN†M68XXX.LOGPHY.ROIN†M68XXX.PAGEALOC.ROIN†M68XXX.PAGEFREE.ROIN†M68XXX.PAUSE.ROIN†M68XXX.POWRFAIL.ROIN†M68XXX.PSTATE.ROIN†M68000.PVSEM.ROIN†M68XXX.RCVSA.ROIN‡M6840.RDTIMER.ROIN†M68XXX.READY.ROIN†M68XXX.RELINQ.ROIN†M68XXX.RESUME.ROIN†M68XXX.REXMON.ROIN†M68XXX.RQSTPA.ROIN†M68XXX.RSTATE.ROIN†M68XXX.RTEVENT.ROIN†M68XXX.SEGALOC.ROIN†M68XXX.SEGDEAL.ROIN†M68XXX.SEGSHAR.ROIN†M68XXX.SELFTEST.ROIN†M68XXX.SERVE.ROIN†M68XXX.SETPRI.ROIN†M68XXX.SGSEM.ROIN†M68000.SINT.ROIN†M68XXX.SNAPTRAC.ROIN†M68XXX.SPURINT.ROIN†M68XXX.STDTIM.ROIN†M68000.SUPER.ROIN†M68XXX.SUSPEND.ROIN†M68XXX.TABLE1.ROIN†M68XXX.TERM.ROIN†M68XXX.TFRSEG.ROIN‡M6840.TIMEINT.ROIN†M68XXX.TRACER.ROIN†M68000.TRAP0.ROIN†M68000.TRAP1.ROIN†M68XXX.TSKATTR.ROIN†M68XXX.TSKBORN.ROIN†M68XXX.TSKINFO.ROIN†M68XXX.TSKMOVE.ROIN†M68XXX.TSKSTART.ROIN†M68XXX.TSKWAIT.ROIN†M68XXX.USERVECT.ROIN†M68XXX.WAKEUP.ROè]ñIN†M68XXX.WTEVENT.ROINPUTƒM68XXX.RMSPATCH.ROEND=ENDéééééé é=/*=/*†Important�note:5=/*†The�order�of�the�INPUT�modules�for�this�LINK�must=/*†be�as�specified�below.=/*=LINK ,INIT,\LINKLS;HAMIXSSEGMENT .INT:8 \INTSTRINPUT M68XXX.INIT.ROINPUT VM01.INITIO.ROINPUT M68XXX.INITDAT.ROINPUT C8OC.SYSPAR.ROEND=ENDééééééù M1VECTTBL ASYST'VM01 XVECTTBLAG7%!ƒRMS68K vector table for the VM01.Š2pPROGINT2 pPROGINT3 pPROGINT4 pPROGINT5 pPROGINT9 pPROGINTA pTIMEINT pSPURINT pTRAP0 pTRAP1 pCOMINT pTRPVCT2 "Pj3?’!VCT(,,,,, , ,,, ,!,"0•4éééé éé'VM02 RMS CD-VECTTBL AG   INITIO1 AG99 INITIO2 AGRR9INITIO AG[[ÖRMS LG||`INT1 LG�� INT2 LG–– VECTTBL ROŸŸC‚******************************************************************$‚*�Sysgen�command�file�VM02.RMS.CD *C‚******************************************************************‚*‚INCLUDE…C8OC.SYSPAR.CI‚*(‰RMS†=�$E00�Address�where�RMS68K�starts.‚*D‚*‚Now�indicate�whether�or�not�the�exec�should�take�over�the�illegalD‚*‚instruction�vector.‚If�you�are�going�to�be�using�the�ROM�debuggerF‚*‚to�set�breakpoints,�then�you'll�want�the�illegal�instruction�vectorC‚*‚left�as�the�debugger�has�it�set.‚In�an�environment�where�the�ROMC‚*‚debugger�will�not�be�used,�you�will�want�RMS68K�to�field�illegal‚*‚instructions�as�exceptions.‚*.‰ILLINSTR�=�1’Illegal�instruction�vector�flag:#‚*¨0�=�RMS�should�not�take�it�over.‚*¨1�=�RMS�should…take�it�over.N‚*****************************************************************************‚**‚*ˆNow�we�generate�the�RMS68K�load�module.‚*N‚*****************************************************************************‚*‚*‚*‚*(‚*‚Now�create�a�VECTTBL�for�this�system.‚*‰SUBS†VM02.VECTTBL.AG4‰ASM‡VM02.VECTTBL.AG,VM02.VECTTBL.RO,VM02.VECTTBL.TF‚*‚*‚Now�link�it�all�together.‚*‰RMS0LO‚=�\RMS‰RMS0HI‚=�\RMS+$FF‰RMS2LO‚=�\RMS+$100‰SUBS†VM02.RMS.LG‚LINKˆVM02.RMS.LG‚=DEL�.&.SYSPAR.RO$‚=COPY‡VM02.VECTTBL.TF,VM02.RMS.LL;A‚=COPY‡SYSGEN.TF,VM02.RMS.LL;A‚=DELƒ*.*.TF;Y‚*‚END‰ éé.  2VECTTBLƒIDNTƒ5,1�RMS68K�vector�table�for�the�VM02.O*v*****************************************************************************O*******************************************************************************O**********************************************************************************É***=***…ROUTINE:‚VECTTBL�--�RMS68K�VECTOR�TABLE�FOR�THE�VM02.Ž******É***J***…ENVIRONMENT:‚Part�of�the�RMS68K�exec�for�the�Motorola�68000�family.***E***‡Copyright�1983�by�Motorola,�Inc.‚This�version�is�for�the�VM02„*** ***‡monoboard�microcomputer.ª******É***E***…FUNCTION:‚This�table�gets�linked�with�RMS68K.‚When�the�system…***C***‡boots,�the�exec�initializer�finds�this�table�and�uses�it�to‡***:***‡take�over�vectors�in�the�processor's�vector�table.�******É***O*******************************************************************************O*******************************************************************************O*^***************************************************************************** *,*‚Revision�history�(add�new�changes�to�top).*…Date†Author‰ChangesG*…--------‚-------------‚----------------------------------------------(*…10/�4/83‚Steve�FranckƒInitial�writing.*  *E*‚XREF's.‚Note�that�there�are�many�more�XREF's�created�by�invocations8*‚of�the�VECTOR�macro;�those�XREF's�are�not�listed�here.*.ŠXREFƒCOMINT�Common�interrupt�handler�routine.   **‚Included�files:*5*‰9995.&.STR.EQ�The�section�number�to�use�is�in�here.*ŠNOLISTŠINCLUDE�9995.&.STR.EQŠLISTŠPAGE*E*‚The�VECTOR�macro�defines�entries�in�the�vector�table.‚The�format�is%*‰VECTOR‚,5*‚There�are�two�special�values�for�:,*‰0�=�COMINT�(the�common�interrupt�handler).(*‰1�=�don't�take�over�the�vector�at�all.E*‚Entries�in�the�vector�table�must�be�assigned�in�order--that�is,�theB*‚vector�#'s�in�the�VECTOR�invocations�must�be�in�ascending�order.H*‚In�the�case�where�two�contiguous�VECTOR�invocations�leave�a�gap�in�the5!<)0K*‚vector�#'s,�those�vector�#'s�in�the�gap�will�be�assigned�the�same�handler9*‚as�that�of�the�lower�vector�#�of�the�pair.‚For�example,+*‰VECTOR�$23,0ŽPoints�$23�to�$27�to�COMINT.-*‰VECTOR�$28,1ŽLeaves�$28�to�$2F�as�they�are.-*‰VECTOR�$30,ROUTINE1‡Points�$30�to�ROUTINE1.G*‚If�the�gap�to�be�filled�has�a�second�parameter�other�than�0�or�1,�theJ*‚address�assigned�to�the�vector�will�be�incremented�by�2�for�each�vector:7*‰VECTOR�$23,XŽPoints�$23�to�X,�$24�to�X+2,�$25�to�X+4.$*‰VECTOR�$26,0ŽPoints�$26�to�COMINT.'*‚The�end�of�the�list�is�signified�by�a*‰DC.Lƒ0F*‚and�the�second�parameter�of�the�last�prior�VECTOR�invocation�will�beK*‚applied�to�all�further�vectors,�up�to�$FF.‚Again,�if�the�second�parameterK*‚was�not�a�0�or�1,�the�address�assigned�to�the�vectors�will�be�incremented#*‚by�2�for�each�vector�in�sequence.* VECTOR„MACROŒIFLEƒ\1-VECT_NUM0ŽFAILƒ499ŒVector�#'s�must�be�in�ascending�order!ŽMEXITŒENDCŒIFNCƒ'\2','0'ŽIFNCƒ'\2','1'�XREFƒ\2ŽENDCŒENDCVECT_NUM„SET„\1ŒDC.Lƒ\1<<24+\2ŠENDM  * *‚First�set�up�the�table�header.*ŠSECTION�LEVEL00  0ŠDC.Lƒ'!VCT'�Dump�eyecatcher�for�'VeCtor�Table.'2ŠDC.LƒCOMINT�Put�the�address�of�COMINT�here�so�the"*§exec�initializer�can�find�it;�he#*§isn't�linked�with�the�exec,�so�he*§wouldn't�know�otherwise.ŠPAGE*)*‚Here�are�the�actual�vector�assignments.I*‚Notice�that�whether�or�not�the�illegal�instruction�vector�is�taken�overE*‚by�RMS68K�is�controlled�by�an�sysgen�parameter.‚During�RMSGEN,�this$*‚parameter�is�substituted�such�thatA*„0�=�the�exec�should�leave�the�illegal�instruction�vector�alone.?*„1�=�the�exec�should�take�over�the�illegal�instruction�vector.J*‚You�might�want�the�exec�to�leave�the�illegal�instruction�vector�alone�ifI*‚you�wa  nt�to�use�the�ROM�debugger,�since�it�uses�illegal�instructions�as*‚breakpoints.* 8VECT_NUM‚SET„1’Initialize�the�vector�number�to�1�so�that&*§the�lowest�vector�number�that�can�be*§set�afterwards�is�2. ŠVECTOR�$02,PROGINT2‡Bus�error.#ŠVECTOR�$03,PROGINT3‡Address�error.$*§If�we're�not�supposed�to�take�over/ŠIFEQƒ\ILLINSTRŠthe�illegal�instruction�vector,9ŠVECTOR�$04,1Žleave�the�illegal�instruction�vector�alone.ŠENDC–*!*§If�we�are�supposed�to�take�over/ŠIFNEƒ\ILLINSTRŠthe�illegal�instruction�vector,>ŠVECTOR�$04,PROGINT4‡take�over�the�illegal�instruction�vector.ŠENDC–*#ŠVECTOR�$05,PROGINT5‡Division�by�0.+*‚in�sequence„$06,PROGINT6ŠCHK�instruction.-*‚in�sequence„$07,PROGINT7ŠTRAPV�instruction./*‚in�sequence„$08,PROGINT8ŠPrivilege�violation.'ŠVECTOR�$09,PROGINT9‡Instruction�trace.8ŠVECTOR�$0A,PROGINTA‡Reserved�instruction�opcodes�$AXXX.>*‚in�sequence„$0B,PROGINTBŠReserved�instruction�opcodes�$FXXX.'ŠVECTOR�$0C,0Ž($0C�-�$17�go�to�COMINT.)'ŠVECTOR�$18,SPURINTˆSpurious�interrupt.'ŠVECTOR�$19,0Ž($19�-�$1B�go�to�COMINT.)*ŠVECTOR�$1C,TIMEINTˆM6840�timer�interrupt.'ŠVECTOR�$1D,0Ž($1D�-�$1E�go�to�COMINT.)8ŠVECTOR�$1F,1ŽSoftware�abort�(leave�it�pointing�to�bug).ŠVECTOR�$20,TRAP0ŠTRAP�#0.ŠVECTOR�$21,TRAP1ŠTRAP�#1.#ŠVECTOR�$22,TRPVCT2ˆTRAP�#2�to�#15.'ŠVECTOR�$30,0Ž($30�-�$8C�go�to�COMINT.)/ŠVECTOR�$8D,POWRFAIL‡ACFAIL*�from�the�VERSAbus.9ŠVECTOR�$8E,KILLER‰This�vector�is�what�you�assign�to�VM02$*§interrupt�sources�you�don't�expect#*§to�go�off;�it�takes�us�to�KILLER.)ŠVECTOR�$8F,0ŽI/O�channel�IRQ1*�(COMINT).)ŠVECTOR�$90,0ŽI/O�channel�IRQ2*�(COMINT).)ŠVECTOR�$91,0ŽI/O�channel�IRQ3*�(COMINT).)ŠVECTOR�$92,0ŽI/O�channel�IRQ4*�(COMINT).<ŠVECTOR�$93,KILLER‰Bus�Clear�interrupt�from�VERSAbus�I/F.‚We%*§shouldn't�be�getting�this,�since�we'*§use�block�transfer�mode�only�if�there%*§are�no�other�potential�bus�masters.0ŠVECTOR�$94,CMRSFAIL‡SYSFAIL*�from�the�VERSAbus. 'ŠVECTOR�$95,0Ž($95�-�$FF�go�to�COMINT.)  !ŠDC.Lƒ0’(End�of�table�indicator.)   ŠEND‰INCLUDE�9999.M6840.M6840.EQ ‰SECTIONƒ8‰XREF†VM02TBL�Found�in�INITIO2‰PAGE*J*‚This�code�is�needed�to�satisfy�INIT,�which�is�board-independent�and�must/*‚call�upon�us�to�do�the�board-dependent�stuff.**„Initialize�the�MMU.*5ŠXDEFƒINITMMUŒIt's�easy�for�us�to�initialize�the�MMU,$INITMMUƒRTS—since�we�don't�have�one. **„Start�the�timer�running.*+ŠXREF.S�CRASHSAV‹These�are�found�in�SYSPAR.ŠXREF.S�EXCSTACKŠXREF.S�PTMADDRŠXREF.S�TIMESLICŠXREF.S�TIMINTVŠXREF.S�TIMINTV4 &ŠXREFƒCLOCKFRQ‹These�are�found�in�IND. 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E*‚>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>•NOTICEš<<<<<<<*‚>>>>>>>µ<<<<<<<>*‚>>>>>>>…When�incorporating�any�drivers�during�SYSGEN„<<<<<<<?*‚>>>>>>>…that�require�memory�allocated�for�them�as�perƒ<<<<<<<?*‚>>>>>>>…the�driver�package�instructions�-�this�is�theƒ<<<<<<<,*‚>>>>>>>…spot�the�file(s)�go�into!!–<<<<<<<*‚>>>>>>>µ<<<<<<<=*‚>>>>>>>…This�is�also�the�spot�for�code�for�a�driver…<<<<<<<>*‚>>>>>>>…that‚requires�other�types�of�initialization,ƒ<<<<<<<0*‚>>>>>>>…such‚as�clearing�an�interrupt.‘<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>‘MERGE�IT�HERE—<<<<<<<*<*ˆWhen�you�write�the�code�that�is�to�be�merged�here,�wrap�it*ˆaround�with�the�following:*:*ˆAt�the�beginning,�with�DRVRxOUT�referring�to�your�unique*ˆlabel,�put�this�code:*'*‹PEA„DRVRxOUT(PC)„IF�BUS�ERROR�OCCURS,*¢RETURN�OR�GO�ON�TO�NEXT*¢DRIVER'S�INITIALIZATION**‹MOVE.W�#'BE',-(A7)…SAVE�'BUS�ERROR'�FLAG*9*ˆThen�insert�the�code�to�do�what�you�need�to�do�for�this*ˆparticular�driver.**ˆAt�the�end,�put�this:***‹LEA„6(A7),A7ˆREMOVE�BUS�ERROR�FROM�STACK*DRVRxOUTƒEQU„**=*ˆIn�this�way,�if�the�code�for�one�driver�causes�a�bus�error,.*ˆthe�code�for�other�drivers�will�be�executed.*E*‚>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<G******  *****************************************************************‰ENDé ‰SECTIONƒ8 ‰XDEF†VM02TBLŠRTS‰PAGE*(*ˆVECTOR�NUMBER�TABLE�FOR�VERSAMODULE-020*ˆTHERE�ARE�3�GROUPS�OF�VECTOR�NUMBERS�STORED�AT%*ˆTHE�HIGH�LOCATIONS�OF�ON�BOARD�RAM.5*ˆTHESE�VECTOR�NUMBERS�ARE�STORED�FROM�TOP�TO�BOTTOM.*ˆTABLE�STRUCTURE:*’DC.W�END�ADDRESS+2�OF�GROUP�X*’DC.W�7TH�VECTOR�NUMBER*’.*’.*’DC.W�1ST�VECTOR�NUMBER* VM02TBLƒEQUƒ* **‚Group�0�vectors.*:‰DC.W‚$1000‰Offset�to�2�+�last�of�group�0�vectors�on�VM02.#‰DC.W�\KILVECT‡IRQ�7-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�6-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�5-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�4-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�3-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�2-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�1-KILLER�ROUTINE **‚Group�1�vectors.*9‰DC.W�$FF0‹Offset�to�2�+�last�of�group�1�vectors�on�VM02.@‰DC.W�\KILVECT‡7�1/3:‚AC�FAIL�from�the�VERSAbus;�send�to�KILLER.+‰DC.W�\SERPTSˆ6�1/3:‚NEC�7201�serial�ports."‰DC.W�\PTMVECT‡5�1/3:‚M6840�timer.:‰DC.W�\BCLRV‰4�1/3:‚Bus�clear…from�VM02�bus�arbiter�logic.@‰DC.W�\KILVECT‡3�1/3:‚Bus�available�from�VM02�bus�arbiter�logic;*«send�to�KILLER.>‰DC.W�\KILVECT‡2�1/3:‚VERSAbus�interrupt�acknowledged;�send�to *«KILLER.-‰DC.W�\FAILŠ1�1/3:‚SYSFAIL�from�the�VERSAbus. **‚Group�2�vectors.*8‰DC.W�$FE0‹Offset�to�2�+�last�of�group�2�vector�on�VM02."‰DC.W�\SWABRTˆIRQ�7-SOFTWARE�ABORT#‰DC.W�\KILVECT‡IRQ�6-KILLER�ROUTINE2‰DC.W�\IOCVEC4‡IRQ�5-I/O�CHANNEL�INTERRUPT�LEVEL�42‰DC.W�\IOCVEC3‡IRQ�4-I/O�CHANNEL�INTERRUPT�LEVEL�32‰DC.W�\IOCVEC2‡IRQ�3-I/O�CHANNEL�INTERRUPT�LEVEL�22‰DC.W�\IOCVEC1‡IRQ�2-I/O�CHANNEL�INTERRUPT�LEVEL�15‰DC.W�\KILVECT‡IRQ�1-KILLER�ROUTINE-UNASSIGNED�VECTOR  ‰ENDéJ:‰INCLUDE�9999.M6840.M6840.EQ ‰SECTIONƒ8‰PAGE*J*‚This�code�is�needed�to�satisfy�INIT,�which�is�board-independent�and�must/*‚call�upon�us�to�do�the�board-dependent�stuff.**„Initialize�the�MMU.*5ŠXDEFƒINITMMUŒIt's�easy�for�us�to�initialize�the�MMU,$INITMMUƒRTS—since�we�don't�have�one. **„Start�the�timer�running.*+ŠXREF.S�CRASHSAV‹These�are�found�in�SYSPAR.ŠXREF.S�EXCSTACKŠXREF.S�PTMADDRŠXREF.S�TIMESLICŠXREF.S�TIMINTVŠXREF.S�TIMINTV4 &ŠXREFƒCLOCKFRQ‹These�are�found�in�IND. ŠXREFƒTIMERAŠXREFƒTIMINTVA ŠXREFƒTIMSLIC 1ŠXDEFƒTIMERSTŒEntry�point�to�START�TIMER�routine.TIMERSTDŠMOVE.L�TIMSLIC(PC),TIMESLIC‚Set�the�sysgen�parameter�which�dictates%*§the�#�of�timer�tics�per�time�slice.'‰MOVE.L�TIMERA(PC),A1‡GET�TIMER�ADDRESS#‰MOVE.L�A1,PTMADDRŠSAVE�IT�FOR�EXEC$‰BEQ.S‚TIMER_EXITŠBRANCH�IF�NO�TIMER)‰PEA„TIMERBE(PC)‰WHERE�TO�GO�ON�BUS�ERROR$‰MOVE.W�#'BE',-(A7)‰SET�BUS�ERR�FLAG3‰MOVE.B�#$01,CR2SR(A1)†ALLOW�WRITE�TO�CONTROL�REG�1&‰MOVE.B�#$01,CR13(A1)‡ALL�TIMERS�RESET$‰MOVE.L�#CLOCKFRQ,D0ˆCLOCK�FREQUENCY‰DIVUƒ#4,D0�DIVIDE�BY�4#‰SUB.W‚#1,D0�CLOCK�INTERRUPTS�AT�-1*‰MOVE.W�TIMINTVA(PC),D1…INTERRUPT�INTERVAL ‰MOVE.W�D1,TIMINTVŠSAVE�FOR�EXEC‰MULUƒ#4,D1�MULTIPLY�BY�4*‰SUB.W‚#1,D1�SUBTRACT�1�-�TI  MER�GOES�TO�-1!‰MOVE.W�D1,TIMINTV4‰SAVE�FOR�EXEC‰LSL.W‚#8,D1�PUT�IN�HIGH�BYTE)‰ADD.W‚D1,D0�VALUE�FOR�TIMER�3�(2�HALVES)‰MOVEP‚D0,MSBT3(A1)ˆSET�TIMER�34‰MOVE.W�#256,D0�VALUE�FOR�TIMER�1�(OVERFLOW�COUNTER)‰MOVEP‚D0,MSBT1(A1)ˆSET�TIMER�18‰MOVE.B�#$00,CR2SR(A1)†ALLOW�WRITE�TO�CONTROL�REGISTER�3;‰MOVE.B�#$C6,CR13(A1)‡T3--INTERNAL�CLOCK,INTERRUPT�ENABLED,*£OUTPUT�ENABLED,�8-BIT�MODE8‰MOVE.B�#$01,CR2SR(A1)†ALLOW�WRITE�TO�CONTROL�REGISTER�1;‰MOVE.B�#$00,CR13(A1)‡T1--EXTERNAL�CLOCK,�ENABLE�ALL�TIMERS3‰ADDQ.L�#6,SP�Everything�went�OK;�just�get�that�bus4‰BRA.S‚TIMER_EXITŠerror�junk�off�the�stack�and�exit.*;TIMERBE‚MOVE.L‚#CRASHSAV,PTMADDR‚USE�DUMP�POINTER�FOR�TIMER TIMER_EXIT�RTS–Return�to�INIT.ŠPAGE ‰XDEF„INITIOS@\2dBl#-‰XREF„CTRLREG…VERSAmodule-02�control�register ‰XREF„MEMTABL4‰XREF„DPRVAO†dual�ported�RAM�VERSAbus�address�offset ‰SECTIONƒ8.************************************************ƒValue�to�put�in�VM02�control�register.ƒ*.***********************************************(CTRL†SET„%000�VERSAbus�int�level�(none).;CTRL†SET„0<<3+CTRLŠVERSAbus�int�acknowledge�mask�(disable).CTRL†SET„1<<10+CTRL‰Write-protect�VM02�RAM�from�VERSAbus?�(no)2CTRL†SET„1<<11+CTRL‰I/O�channel�int�mask�(enable).@CTRL†SET„%0000<<12+CTRL…Address�modifiers�for�VERSAbus�accesses. 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**‚Group�0�vectors.*:‰DC.W‚$1000‰Offset�to�2�+�last�of�group�0�vectors�on�VM02.#‰DC.W�\KILVECT‡IRQ�7-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�6-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�5-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�4-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�3-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�2-KILLER�ROUTINE#‰DC.W�\KILVECT‡IRQ�1-KILLER�ROUTINE **‚Group�1�vectors.*9‰DC.W�$FF0‹Offset�to�2�+�last�of�group�1�vectors�on�VM02.@‰DC.W�\KILVECT‡7�1/3:‚AC�FAIL�from�the�VERSAbus;�send�to�KILLER.+‰DC.W�\SERPTSˆ6�1/3:‚NEC�7201�serial�ports."‰DC.W�\PTMVECT‡5�1/3:‚M6840�timer.:‰DC.W�\BCLRV‰4�1/3:‚Bus�clear…from�VM02�bus�arbiter�logic.@‰DC.W�\KILVECT‡3�1/3:‚Bus�available�from�VM02�bus�arbiter�logic;*«send�to�KILLER.>‰DC.W�\KILVECT‡2�1/3:‚VERSAbus�interrupt�acknowledged;�send�to *«KILLER.-‰DC.W�\FAILŠ1�1/3:‚SYSFAIL�from�the�VERSAbus. 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for�this�system.‚*‰SUBS†VMES10.VECTTBL.AG:‰ASM‡VMES10.VECTTBL.AG,VMES10.VECTTBL.RO,VMES10.VECTTBL.TF‚*‚*‚Now�link�it�all�together.‚*‰RMS0LO‚=�\RMS‰RMS0HI‚=�\RMS+$FF‰RMS2LO‚=�\RMS+$100‰SUBS†VMES10.RMS.LG‚LINKˆVMES10.RMS.LG‚=DEL�.&.SYSPAR.RO(‚=COPY‡VMES10.VECTTBL.TF,VMES10.RMS.LL;A ‚=COPY‡SYSGEN.TF,VMES10.RMS.LL;A‚=DELƒ*.*.TF;Y‚*‚END‰ éé¤.4VECTTBLƒIDNTƒ5,1�RMS68K�vector�table�for�the�VME/10.O*v*****************************************************************************O*******************************************************************************O**********************************************************************************É***>***…ROUTINE:‚VECTTBL�--�RMS68K�VECTOR�TABLE�FOR�THE�VME/10�******É***J***…ENVIRONMENT:‚Part�of�the�RMS68K�exec�for�the�Motorola�68000�family.***G***‡Copyright�1983�by�Motorola,�Inc.‚This�version�is�for�the�VME/10‚***"***‡microcomputer�workstation.¨******É***E***…FUNCTION:‚This�table�gets�linked�with�RMS68K.‚When�the�system…***C***‡boots,�the�exec�initializer�finds�this�table�and�uses�it�to‡***:***‡take�over�vectors�in�the�processor's�vector�table.�******É***O*******************************************************************************O*******************************************************************************O*^***************************************************************************** *,*‚Revision�history�(add�new�changes�to�top).*…Date†Author‚Changes@*…--------‚------‚----------------------------------------------*…10/24/83ƒSJF„Initial�writing.*  *E*‚XREF's.‚Note�that�there�are�many�more�XREF's�created�by�invocations8*‚of�the�VECTOR�macro;�those�XREF's�are�not�listed�here.*.ŠXREFƒCOMINT�Common�interrupt�handler�routine.   **‚Included�files:*5*‰9995.&.STR.EQ�The�section�number�to�use�is�in�here.*ŠNOLISTŠINCLUDE�9995.&.STR.EQŠLISTŠPAGE*E*‚The�VECTOR�macro�defines�entries�in�the�vector�table.‚The�format�is%*‰VECTOR‚,5*‚There�are�two�special�values�for�:,*‰0�=�COMINT�(the�common�interrupt�handler).(*‰1�=�don't�take�over�the�vector�at�all.E*‚Entries�in�the�vector�table�must�be�assigned�in�order--that�is,�theB*‚vector�#'s�in�the�VECTOR�invocations�must�be�in�ascending�order.H*‚In�the�case�where�two�contiguous�VECTOR�invocations�leave�a�gap�in�the­5¶<¾.Æ K*‚vector�#'s,�those�vector�#'s�in�the�gap�will�be�assigned�the�same�handler9*‚as�that�of�the�lower�vector�#�of�the�pair.‚For�example,+*‰VECTOR�$23,0ŽPoints�$23�to�$27�to�COMINT.-*‰VECTOR�$28,1ŽLeaves�$28�to�$2F�as�they�are.-*‰VECTOR�$30,ROUTINE1‡Points�$30�to�ROUTINE1.G*‚If�the�gap�to�be�filled�has�a�second�parameter�other�than�0�or�1,�theJ*‚address�assigned�to�the�vector�will�be�incremented�by�2�for�each�vector:7*‰VECTOR�$23,XŽPoints�$23�to�X,�$24�to�X+2,�$25�to�X+4.$*‰VECTOR�$26,0ŽPoints� $26�to�COMINT.'*‚The�end�of�the�list�is�signified�by�a*‰DC.Lƒ0F*‚and�the�second�parameter�of�the�last�prior�VECTOR�invocation�will�beK*‚applied�to�all�further�vectors,�up�to�$FF.‚Again,�if�the�second�parameterK*‚was�not�a�0�or�1,�the�address�assigned�to�the�vectors�will�be�incremented#*‚by�2�for�each�vector�in�sequence.* VECTOR„MACROŒIFLEƒ\1-VECT_NUM0ŽFAILƒ499ŒVector�#'s�must�be�in�ascending�order!ŽMEXITŒENDCŒIFNCƒ'\2','0'ŽIFNCƒ'\2','1'�XREFƒ\2ŽENDCŒENDCVECT_NUM„SET„\1ŒDC.Lƒ\1<<24+\2ŠENDM  * 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&‰MOVE.L‚MMU(PC),MMUHERE†ADDRESS�OF�MMU‰BEQ.SƒN68451XŽBRANCH�IF�NO�MMU#‰MOVE.L‚MMU(PC),A0‹A0�-->�FIRST�MMU(‰PEA…KILLER�CRASH�IF�FIRST�MMU�NOT�THERE'‰MOVE.W‚#'BE',-(A7)ŠBUS�ERROR�SWITCH�ON,‰MOVE.B‚(A0),D0ŽVERIFY�PRESENCE�OF�FIRST�MMU8‰MOVE.L‚A0,FRST451‹SAVE�ADDRESS�OF�FIRST�68451�IN�SYSPAR.‰MOVE.L‚A0,CURR451‹IT'S�ALSO�THE�CURRENT�68451(‰MOVE.L‚#1,CURRSDŒSEGMENT�DESCRIPTOR�#�1#‰LEA…N68451U(PC),A1‡ADDRESS�OF�EXIT6‰MOVE.L‚A1,2(A7)�EXIT�IF�BUS�ERROR�WHILE�COUNTING�MMUs%‰MOVE.W‚#3,D0�FOUR�POSSIBLE�LAST�MMUsN68451B1‰MOVE.B‚(A0),D1ŽEXIT�THROUGH�BUS�ERROR�IF�NO�NEXT.‰MOVE.L‚A0,LAST451‹CURRENT�MAY�BE�THE�LAST�MMU)‰ADD.Lƒ#$40,A0ŽSET�TO�CHECK�NEXT�MMU�SLOT‰DBRA„D0,N68451B‹LOOP�TILL�DONE+‰ADD.Lƒ#6,A7�BUS�ERROR�POINTER�OFF�OF�STACK *I*‚Unload�segment�descripters�in�all�MMU's,�in�case�RESET�wasn't�performed*‚prior�to�boot.*N68451U'ŠMOVE.L�FRST451,A1ŠPoint�to�first�68451$ŠMOVE.B�#1,D0�Segment�descriptor�#�1UNLD10%ŠMOVE.B�D0,DP(A1)‹Point�to�descriptor-ŠMOVE.B�#0,SSR(A1)ŠElse�clear�this�descriptorUNLDNEXTŠADDQ.B�#1,D0�Next�descriptorŠCMP.B‚#$20,D0�End�of�this�MMU?ŠBNE.S‚UNLD10ŽBranch�if�no#ŠLEA„$40(A1),A1ŠMove�on�to�next�MMUŠCLR.B‚D0’Descriptor�#�0)ŠCMP.L‚LAST451,A1ŠAre�we�beyond�all�MMUs?ŠBLE.S‚UNLD10ŽBranch�if�noUNLDEXIT **‚Exit.*9N68451XƒRESTORE�D0/D1/A0/A1‡Restore�registers�and�return.ŠRTS—*ŠPAGEO*********************************************************************************ˆSTART�TIMER„(146818�TIMER)* *G*‚This�macro�will�verify�that�a�byte�is�within�a�specified�range.‚If�itH*‚is�not�within�the�range,�a�branch�is�taken�to�RANGE_ERR.‚The�syntax�isD*„CHECK_RANGE.‚,,F*‚Distance�is�S�for�short�branches,�L�for�long�branches,�or�nothing�if*‚the�default�will�do.6*‚The�byte�to�check�is�treated�as�an�unsigned�integer.*CHECK_RANGE MACRO ŠCMP.B‚\2,\1ŠBLO.\0�RANGE_ERR ŠCMP.B‚\3,\1ŠBHI.\0�RANGE_ERRŠENDM  TIMERST:E‰MOVE.L�TIMSLIC(PC),TIMESLIC‚#�TIMER�INTERRUPTS�BEFORE�TASK�INTERRUPT'‰MOVE.L�TIMERA(PC),A1‡GET�TIMER�ADDRESS#‰MOVE.L�A1,PTMADDRŠSAVE�IT�FOR�EXEC!‰BEQ.L‚TIMERBE�BRANCH�IF�NO�TIMER)‰PEA„TIMERBE(PC)‰WHERE�TO�GO�ON�BUS�ERROR$‰MOVE.W�#'BE',-(A7)‰SET�BUS�ERR�FLAG*4*ˆGet�system�time�and�date�from�battery�backed�timer* UIP_LOOP:0‰BTST†#7,REGA�Wait�until�UIP�bit�is�clear�before#‰BNE.S…UIP_LOOPŒreading�timer�chip. *‰CLR.L…D1’Prepare�for�following�short�load'‰MOVE.B„HRS(A1),D1ŠGet�hours�from�timerŠCHECK _RANGE.L�D1,#0,#230‰MOVE.L„#3600*1000,D2‡Addend�is�one�hour's�msecs+‰CLR.L…D0’Calculation�will�take�place�in�D0*‰BRA.S…CALCLOOPŒStart�the�calculation�loopCALCHRS)‰ADD.L…D2,D0�Add�one�hour's�msecs�to�timeCALCLOOP*‰DBRA†D1,CALCHRSŠLoop�until�hours�computed*‰CLR.W…D1’Prepare�for�following�short�load*‰MOVE.B„MINS(A1),D1‰Get�minutes�from�timerŠCHECK_RANGE�D1,#0,#59)‰MULU.W„#60,D1ŽConvert�minutes�to�seconds*‰CLR.L…D2’Prepare�for�following�short�load*‰MOVE.B„SECS(A1),D2‰Get�seconds�from�timerŠCHECK_RANGE�D2,#0,#59‰ADD.L…D2,D1�D1=total�seconds‰MULU.W„#1000,D1ŒD1=total�msecs!‰ADD.L…D1,D0�D0=grand�total�msecs#‰MOVE.L„D0,TIMEOD‹Store�it�for�exec (‰CLR.L…D0’Prepare�to�form�gregorian�date'‰MOVE.B„YEAR(A1),D0‰Get�year�from�timerŠCHECK_RANGE�D0,#0,#99‰ADD.W…#1900,D0ŒYear=1900+YY‰SWAP†D0’D0=YYYY0000 ‰MOVE.B„MONTH(A1),D0ˆD0=YYYY00MMŠCHECK_RANGE�D0,#1,#12‰LSL.W…#8,D0�D0=YYYYMM00"‰MOVE.B„DAYOMTH(A1),D0†D0=YYYYMMDDŠCHECK_RANGE�D0,#1,#31 *I*‚The�time�and�date�look�reasonable,�so�let's�go�ahead�and�keep�those�forG*‚our�own�(the�chip�must�not�have�lost�power�since�last�time).‚We�can'tI*‚tell�for�sure�whether�the�chip�lost�power,�even�though�there's�a�bit�inJ*‚the�chip�that�says�so,�because�the�bug�has�already�read�the�information,*‚making�it�unavailable�to�us.* ‰BSR.L…DATEGOŽConvert�to�ordinal!‰MOVE.L„D0,DATE�Give�date�to�exec ŠBRA.S‚GO_TIMER *H*‚If�we�come�here,�one�of�the�fields�read�from�the�clock�chip�is�whacko.*‚Set�system�time�and�day�to�0.*-RANGE_ERR�MOVE.L�#0,TIMEODŠTime�of�day�<--�0.ŠMOVE.L�#0,DATEŒDate�<--�0. **ˆNow�start�timer�ticking*KGO_TIMER�MOVEƒTIMINTVA(PC),TIMINTV‚Save�timer�interrupt�interval�in�SYSPAR.4‰MOVE.B�#$A,REGA(A1)ˆSELECT�PERIODIC�ACTIVATION�RATE0‰MOVE.B�REGC(A1),D0‰RESET�ANY�PENDING�INTERRUPTS&‰MOVE.B�#$46,REGB(A1)‡ENABLE�THE�TIMER.‰ADD.L‚#6,A7�REMOVE�'BE'�AND�BUS�ERROR�ADDRESS‰RTS˜BACK�TO�INIT*CTRL1…SET„%00<<5+CTRL1‡Cursor�selection�(we�leave�this�alone).CTRL1…SET„0<<7+CTRL1‰Reserved.  0************************************************,*ƒValue�to�put�in�VMEC1�control�register�2ƒ*0************************************************ 0CTRL2…SET„0<<0�Mask�for�MMU�interrupt�(disable).;CTRL2…SET„0<<1+CTRL2‰Mask�for�'transmitter�empty'�interrupt$*§from�the�2661�connecting�us�to�the*§keyboard�(disable).>CTRL2…SET„0<<2+CTRL2‰Mask�for�'bus�clear'�interrupt�(disable).CTRL5…SET„1<<4+CTRL5‰Mask�for�local�resource�timeout�(enable).6CTRL5…SET„1<<5+CTRL5‰Mask�for�VMEbus�timeout�(enable).;CTRL5…SET„0<<6+CTRL5‰Address�modifier�alteration�(disable).=CTRL5…SET„1<<7+CTRL5‰Board�fail�control�(we're�OK).‚When�this'*§bit�is�0,�SYSFAIL*�is�asserted�on�the *§VMEbus.  0************************************************,*ƒValue�to�put�in�VMEC1�control�register�6ƒ*0************************************************ >>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>•NOTICEš<<<<<<<*‚>>>>>>>µ<<<<<<<>*‚>>>>>>>…When�incorporating�any�drivers�during�SYSGEN„<<<<<<<?*‚>>>>>>>…that�require�memory�allocated�for�them�as�perƒ<<<<<<<?*‚>>>>>>>…the�driver�package�instructions�-�this�is�theƒ<<<<<<<,*‚>>>>>>>…spot�the�file(s)�go�into!!–<<<<<<<*‚>>>>>>>µ<<<<<<<=*‚>>>>>>>…This�is�also�the�spot�for�code�for�a�driver…<<<<<<<>*‚>>>>>>>…that‚requires�other�types�of�initialization,ƒ<<<<<<<0*‚>>>>>>>…such‚as�clearing�an�interrupt.‘<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>‘MERGE�IT�HERE—<<<<<<<*<*ˆWhen�you�write�the�code�that�is�to�be�merged�here,�wrap�it*ˆaround�with�the�following:*:*ˆAt�the�beginning,�with�DRVRxOUT�referring�to�your�unique*ˆlabel,�put�this�code:*'*‹PEA„DRVRxOUT(PC)„IF�BUS�ERROR�OCCURS,*¢RETURN�OR�GO�ON�TO�NEXT*¢DRIVER'S�INITIALIZATION**‹MOVE.W�#'BE',-(A7)…SAVE�'BUS�ERROR'�FLAG*9*ˆThen�insert�the�code�to�do�what�you�need�to�do�for�this*ˆparticular�driver.**ˆAt�the�end,�put�this:***‹LEA„6(A7),A7ˆREMOVE�BUS�ERROR�FROM�STACK*DRVRxOUTƒEQU„**=*ˆIn�this�way,�if�the�code�for�one�driver�causes�a�bus�error,.*ˆthe�code�for�other�drivers�will�be�executed.*E*‚>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<G***********************************************************************G***********************************************************************‰ENDéééééééO*********************************************************************************ˆVMES10.INITIO2.AG*O******************************************************************************* ‰SECTIONƒ8ŠRTS‰PAGE O****************************** *************************************************2*ˆDATE�CONVERSIONS�FROM�ONE�BINARY�FORM�TO�ANOTHER*Ç6*ˆORDINAL�DATE�-->�DAY�NUMBER�WHERE�DAY�1�=�JAN�1�1980***ˆCALL *’BSR‡DATEGO*¦BINARY�GREGORIAN�-�YYYYMMDD*§TO*¦BINARY�ORDINALƒ-�DAY�NUMBER*ˆINPUT'*’D0�=�DATE�TO�BE�CONVERTED�--�YYYYMMDD**ˆOUTPUT#*’D0�=�CONVERTED�DATE‡--�DAY�NUMBER*O******************************************************************************* ‰SECTIONƒ8**ˆNON-LEAP�DAYS�BEFORE�TABLE¥*Ç=DATEDBNL�DC.W�0,31,59,90,120,151,181,212,243,273,304,334,365Œ*Ç*ˆLEAP�DAYS�BEFORE�TABLE©*Ç�FIRST�MMU(‰PEA…KILLER�CRASH�IF�FIRST�MMU�NOT�THERE'‰MOVE.W‚#'BE',-(A7)ŠBUS�ERROR�SWITCH�ON,‰MOVE.B‚(A0),D0ŽVERIFY�PRESENCE�OF�FIRST�MMU8‰MOVE.L‚A0,FRST451‹SAVE�ADDRESS�OF�FIRST�68451�IN�SYSPAR.‰MOVE.L‚A0,CURR451‹IT'S�ALSO�THE�CURRENT�68451(‰MOVE.L‚#1,CURRSDŒSEGMENT�DESCRIPTOR�#�1#‰LEA…N68451X(PC),A1‡ADDRESS�OF�EXIT6‰MOVE.L‚A1,2(A7)�EXIT�IF�BUS�ERROR�WHILE�COUNTING�MMUs%‰MOVE.W‚#3,D0�FOUR�POSSIBLE�LAST�MMUsN68451B1‰MOVE.B‚(A0),D1ŽEXIT�THROUGH�BUS�ERROR�IF�NO�NEXT.‰MOVE.L‚A0,LAST451‹CURRENT�MAY�BE�THE�LAST�MMU)‰ADD.Lƒ#$40,A0ŽSET�TO�CHECK�NEXT�MMU�SLOT‰DBRA„D0,N68451B‹LOOP�TILL�DONE+‰ADD.Lƒ#6,A7�BUS�ERROR�POINTER�OFF�OF�STACKN68451X‰RTSšBACK�TO�INIT‰PAGE**ˆSTART�TIMER„(146818�TIMER)*‰XREF†CRASHSAV‰XREF.S„TIMESLIC‰XREF.S„TIMINTV‰XREF.S„TIMINTV4‰XREF.S„PTMADDR ‰XREF†TIMSLIC‰XREF†TIMERA,TIMINTVA‰XREF†CLOCKFRQ* ‰XDEFƒTIMERSTTIMERSTE‰MOVE.L�TIMSLIC(PC),TIMESLIC‚#�TIMER�INTERRUPTS�BEFORE�TASK�INTERRUPT'‰MOVE.L�TIMERA(PC),A1‡GET�TIMER�ADDRESS#‰MOVE.L�A1,PTMADDRŠSAVE�IT�FOR�EXEC‰BEQ„TIMERBE�BRANCH�IF�NO�TIMER)‰PEA„TIMERBE(PC)‰WHERE�TO�GO�ON�BUS�ERROR$‰MOVE.W�#'BE',-(A7)‰SET�BUS�ERR�FLAG*4*ˆGet�system�time�and�date�from�battery�backed�timer*6‰MOVE.B„REGD(A1),D1‰Read�regd�just�to�insure�VRT�is�on6‰MOVE.B„#$82,REGB(A1)‡Be�sure�no�updates,�24�hour�modeTIMERWT(O1>9BA#/‰BTST†#7,REGA(A1)‰Is�an�update�in�progress�now?‰BNE.S…TIMERWT�Branch�if�yes *‰CLR.L…D1’Prepare�for�following�short�load'‰MOVE.B„HRS(A1),D1ŠGet�hours�from�timer0‰MOVE.L„#3600*1000,D2‡Addend�is�one�hour's�msecs+‰CLR.L…D0’Calculation�will�take�place�in�D0*‰BRA.S…CALCLOOPŒStart�the�calculation�loopCALCHRS)‰ADD.L…D2,D0�Add�one�hour's�msecs�to�timeCALCLOOP*‰DBRA†D1,CALCHRSŠLoop�until�hours�computed*‰CLR.W…D1’Prepare�for�following�short�load*‰MOVE.B„MINS(A1),D1‰Get�minutes�from�timer)‰MULU.W„#60,D1ŽConvert�minutes�to�seconds*‰CLR.L…D2’Prepare�for�following�short�load*‰MOVE.B„SECS(A1),D2‰Get�seconds�from�timer‰ADD.L…D2,D1�D1=total�seconds‰MULU.W„#1000,D1ŒD1=total�msecs!‰ADD.L…D1,D0�D0=grand�total�msecs#‰MOVE.L„D0,TIMEOD‹Store�it�for�exec (‰CLR.L…D0’Prepare�to�form�gregorian�date'‰MOVE.B„YEAR(A1),D0‰Get�year�from�timer‰ADD.W…#1900,D0ŒYear=1900+YY‰SWAP†D0’D0=YYYY0000 ‰MOVE.B„MONTH(A1),D0ˆD0=YYYY00MM‰LSL.W…#8,D0�D0=YYYYMM00"‰MOVE.B„DAYOMTH(A1),D0†D0=YYYYMMDD‰BSR‡DATEGOŽConvert�to�ordinal!‰MOVE.L„D0,DATE�Give�date�to�exec**ˆNow�start�timer�ticking**‰MOVE.W�TIMINTVA(PC),D1…INTERRUPT�INTERVAL ‰MOVE.W�D1,TIMINTVŠSAVE�FOR�EXEC4‰MOVE.B�#$A,REGA(A1)ˆSELECT�PERIODIC�ACTIVATION�RATE0‰MOVE.B�REGC(A1),D0‰RESET�ANY�PENDING�INTERRUPTS&‰MOVE.B�#$46,REGB(A1)‡ENABLE�THE�TIMER.‰ADD.L‚#6,A7�REMOVE�'BE'�AND�BUS�ERROR�ADDRESS‰RTS˜BACK�TO�INIT*>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>•NOTICEš<<<<<<<*‚>>>>>>>µ<<<<<<<>*‚>>>>>>>…When�incorporating�any�drivers�during�SYSGEN„<<<<<<<?*‚>>>>>>>…that�require�memory�allocated�for�them�as�perƒ<<<<<<<?*‚>>>>>>>…the�driver�package�instructions�-�this�is�theƒ<<<<<<<,*‚>>>>>>>…spot�the�file(s)�go�into!!–<<<<<<<*‚>>>>>>>µ<<<<<<<*‚>>>>>>>µ<<<<<<<E*‚>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<)ŠLEA„6(A7),A7‡REMOVE�BUS�ERROR�FROM�STACK INITIORƒRTSO*******************************************************************************2*ˆDATE�CONVERSIONS�FROM�ONE�BINARY�FORM�TO�ANOTHER*Ç6*ˆORDINAL�DATE�-->�DAY�NUMBER�WHERE�DAY�1�=�JAN�1�1980***ˆCALL *’BSR‡DATEGO*¦BINARY�GREGORIAN�-�YYYYMMDD*§TO*¦BINARY�ORDINALƒ-�DAY�NUMBER*ˆINPUT'*’D0�=�DATE�TO�BE�CONVERTED�--�YYYYMMDD**ˆOUTPUT#*’D0�=�CONVERTED�DATE‡--�DAY�NUMBER*O*********************************************************************************ˆNON-LEAP�DAYS�BEFORE�TABLE¥*Ç=DATEDBNL�DC.W�0,31,59,90,120,151,181,212,243,273,304,334,365Œ*Ç*ˆLEAP�DAYS�BEFORE�TABLE©*Ç,5*‚There�are�two�special�values�for�:,*‰0�=�COMINT�(the�common�interrupt�handler).(*‰1�=�don't�take�over�the�vector�at�all.E*‚Entries�in�the�vector�table�must�be�assigned�in�order--that�is,�theB*‚vector�#'s�in�the�VECTOR�invocations�must�be�in�ascending�order.H*‚In�the�case�where�two�contiguous�VECTOR�invocations�leave�a�gap�in�the‚5‹<“3K*‚vector�#'s,�those�vector�#'s�in�the�gap�will�be�assigned�the�same�handler9*‚as�that�of�the�lower�vector�#�of�the�pair.‚For�example,+*‰VECTOR�$23,0ŽPoints�$23�to�$27�to�COMINT.-*‰VECTOR�$28,1ŽLeaves�$28�to�$2F�as�they�are.-*‰VECTOR�$30,ROUTINE1‡Points�$30�to�ROUTINE1.G*‚If�the�gap�to�be�filled�has�a�second�parameter�other�than�0�or�1,�theJ*‚address�assigned�to�the�vector�will�be�incremented�by�2�for�each�vector:7*‰VECTOR�$23,XŽPoints�$23�to�X,�$24�to�X+2,�$25�to�X+4.$*‰VECTOR�$26,0ŽPoints�$26�to�COMINT.'*‚The�end�of�the�list�is�signified�by�a*‰DC.Lƒ0F*‚and�the�second�parameter�of�the�last�prior�VECTOR�invocation�will�beK*‚applied�to�all�further�vectors,�up�to�$FF.‚Again,�if�the�second�parameterK*‚was�not�a�0�or�1,�the�address�assigned�to�the�vectors�will�be�incremented#*‚by�2�for�each�vector�in�sequence.* VECTOR„MACROŒIFLEƒ\1-VECT_NUM0ŽFAILƒ499ŒVector�#'s�must�be�in�ascending�order!ŽMEXITŒENDCŒIFNCƒ'\2','0'ŽIFNCƒ'\2','1'�XREFƒ\2ŽENDCŒENDCVECT_NUM„SET„\1ŒDC.Lƒ\1<<24+\2ŠENDM  * *‚First�set�up�the�table�header.*ŠSECTION�LEVEL00  0ŠDC.Lƒ'!VCT'�Dump�eyecatcher�for�'VeCtor�Table.'2ŠDC.LƒCOMINT�Put�the�address�of�COMINT�here�so�the"*§exec�initializer�can�find�it;�he#*§isn't�linked�with�the�exec,�so�he*§wouldn't�know�otherwise.ŠPAGE*)*‚Here�are�the�actual�vector�assignments.I*‚Notice�that�whether�or�not�the�illegal�instruction�vector�is�taken�overE*‚by�RMS68K�is�controlled�by�an�sysgen�parameter.‚During�RMSGEN,�this$*‚parameter�is�substituted�such�thatA*„0�=�the�exec�should�leave�the�illegal�instruction�vector�alone.?*„1�=�the�exec�should�take�over�the�illegal�instruction�vector.J*‚You�might�want�the�exec�to�leave�the�illegal�instruction�vector�alone�ifI*‚you�want�to�use�the�ROM�debugger,�since�it�uses�illegal�instructions�as*‚breakpoints.* 8VECT_NUM‚SET„1’Initialize�the�vector�number�to�1�so�that&*§the�lowest�vector�number�that�can�be*§set�afterwards�is�2. ŠVECTOR�$02,PROGINT2‡Bus�error.#ŠVECTOR�$03,PROGINT3‡Address�error.$*§If�we're�not�supposed�to�take�over/ŠIFEQƒ\ILLINSTRŠthe�illegal�instruction�vector,9ŠVECTOR�$04,1Žleave�the�illegal�instruction�vector�alone.ŠENDC–*!*§If�we�are�supposed�to�take�over/ŠIFNEƒ\ILLINSTRŠthe�illegal�instruction�vector,>ŠVECTOR�$04,PROGINT4‡take�over�the�illegal�instruction�vector.ŠENDC–*#ŠVECTOR�$05,PROGINT5‡Division�by�0.+*‚in�sequence„$06,PROGINT6ŠCHK�instruction.-*‚in�sequence„$07,PROGINT7ŠTRAPV�instruction./*‚in�sequence„$08,PROGINT8ŠPrivilege�violation.'ŠVECTOR�$09,PROGINT9‡Instruction�trace.8ŠVECTOR�$0A,PROGINTA‡Reserved�instruction�opcodes�$AXXX.>*‚in�sequence„$0B,PROGINTBŠReserved�instruction�opcodes�$FXXX.'ŠVECTOR�$0C,0Ž($0C�-�$17�go�to�COMINT.)'ŠVECTOR�$18,SPURINTˆSpurious�interrupt.'ŠVECTOR�$19,0Ž($19�-�$1F�go�to�COMINT.)ŠVECTOR�$20,TRAP0ŠTRAP�#0.ŠVECTOR�$21,TRAP1ŠTRAP�#1.#ŠVECTOR�$22,TRPVCT2ˆTRAP�#2�to�#15.'ŠVECTOR�$30,0Ž($30�-�$3F�go�to�COMINT.)0ŠVECTOR�$40,CMRSFAIL‡SYSFAIL*�from�the�VERSAbus.<ŠVECTOR�$41,KILLER‰Acknowledgement�of�interrupt�to�VERSAbus;%*§We�mask�this�interrupt,�so�we�don't*§expect�to�use�this�vector.<ŠVECTOR�$42,KILLER‰Bus�Clear�interrupt�from�VERSAbus�I/F.‚We%*§shouldn't�be�getting�this,�since�we'*§use�block�transfer�mode�only �if�there%*§are�no�other�potential�bus�masters.-ŠVECTOR�$43,0ŽNEC�7201�serial�ports�(COMINT).,ŠVECTOR�$44,TIMEINTˆM146818�real�time�clock.7ŠVECTOR�$45,0ŽM6840�programmable�timer�module�(COMINT)./ŠVECTOR�$46,POWRFAIL‡ACFAIL*�from�the�VERSAbus.9ŠVECTOR�$47,KILLER‰M68451�memory�management�unit.‚Getting'*§one�of�these�means�something's�wrong.#ŠVECTOR�$48,0Ž($48�goes�to�COMINT.))ŠVECTOR�$49,0ŽI/O�channel�IRQ1*�(COMINT).)ŠVECTOR�$4A,0ŽI/O�channel�IRQ2*�(COMINT).)ŠVECTOR�$4B,0ŽI/O�channel�IRQ3*�(COMINT).)ŠVECTOR�$4C,0ŽI/O�channel�IRQ4*�(COMINT).8ŠVECTOR�$4D,1ŽSoftware�abort�(leave�it�pointing�to�bug).'ŠVECTOR�$4E,0Ž($4E�-�$FF�go�to�COMINT.)  !ŠDC.Lƒ0’(End�of�table�indicator.)   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