IMD 1.16: 5/06/2007 17:29:58 64620-12006 Rev. 2421A State Analyzer 2 of 2  D #?DGC} *4 N64620-12006 STATE SRS ABSOLUTE S-64620-12006-1 RVA 0202 DESIGNER BRYCE GOODWIN 2421 HEWLETT PACKARD                            ! " !#"$  #%$&  %'&(  ')(*  )+*,  +-,.  -/.0  /102  1324  3546  5768 798: 9;:< ;=<> =?>@ ?A@B ACBB database HP GG + +pv_am1100HP VVgpv_prepF0HP [\D@pv_prep80HP WZ @ssmmtmp3 HP(hp)[\ + +pv_64620 HP HU5  ]Cg}AD PV_STATE 16 May 1984 21  pv_64620 :HP :0001H  pv_am1100:HP :0001H  pv_prep80:HP :0001H  pv_prepF0:HP :0001H  ' ;<D`[LtUihp@llllllPass Fail 76543210 98765432109876543210 (1 = Error)q0q,uB2, 1 t52u<3o01ŜuError: System softwardatabase was not upded (file tapebase:HPot found) Fަ9B3D4DNDDD4BBBt B5EE9tD6B5Searching for AIMB stimulus boardsAwaiting command 7D8D8D 7D A72&B (L A0(CBqh|j0830B3qxuqq}lKoKo3 L7'3Ί7/\'L D8Al Dh-0oo 3G2 A7fL3 (A dD[oD2 ?VK3Sl A9 C5" 0D0quqq}lo]ol=lA74 5 A7.59 (LtB (LAڑ:l& D8Ao D(L (LްLDG (L`Ұpv_prep00HP  %|3%y3DKK& C0 L A30qxuqq}loKK[oDoӳB3B3Du CDf"l:%DKKLoc8AoD D A0%&}0$qqqit~0830qxuqq}loKo~08qx(Ll:&l(8HoA2& (L:&o.i'3DlD9&=t :%\"&3҈G&"R*&0o1{5A3z  A64$# l l $AA:lB D D!pv_am0000HPA6L0 00l"ll#kl%jl&il'hl-gl)fl)el3( ,b A345AB#’TToBRRoQQoPo0AJoIoBIAHHCGBEA Dl@BB 58|oғIntermodule Bus might not be reset, slot 0 (reset at power up)&FA`A@.D@@`O@(@8@0@@CB`euBB L}BBPA,G}BB`tlE$0 D4CBCG48l5$ '"(A8BqitB7777K7Ȓ;l<^ A9l;l?5LlAUlA]=| B5DW@Z[^BǞotgt7soDl$OkD<4A7mD"C7ddCDDIH\0MOYXMl " uXo7NA7SB7IoDA7LC'A'J CAA C<B@9g777B74 /,/3G' ]u>ECl WlGCD/lk 0 C0DXllbqxuHo@Slot "“Z@Preproc "“[`@PASSED@FAILEDu 10 MHz Verification PASSEDSlot nn, Test nnin process A6AAD 3Ŕe˔A;(AeRA[ˊByi(8XoCDEF@10 MHz State Test: A@ Configuration pHQDiH(@includedDj4x3Q3 373M33D8[lA 3[lG383L3D#[lA4L 3[lH383B3D A j3[ot 7tAll4 L<3Al$ }#Ѐ/;3B 7tAA;#3 |;lB&A;"3A j3[lKKoQDiH(@excludedFHDjpP ` `  `@preproc ` `Ih2I╵` ` `Dh"`Dj` ` H@am @:HP IpP`@preproc ` `H@prep @:HP ? Slot ID  Description Part Number Boards for IMB testingFile not found: pv_10 MHz boards A3Q3 373΃tl!'3BAA; M3"3 #р'P3A j3[lKKo3Q3 373΃tl M0 I3 C3 C3A j3[lKKo@All Boards Test Summary pPPDPʀ` ` @preproc `  `"`IpP8#`#`աHkHn Slot ID #Tests Description Tested Failed Last DRB4GlDLB/DHB,DDB)D@BA6D9`!DG"|@A6D(#oA6D!˼GG̼oAABBDEFGHIKLMNJOpPRhhh`oL0 *lL0 ;PQA6GF0O3η|~XoD^UUUUA6GD0OJͷXoXoGBA6GR8BDXoaB`PQ﷬GHA67GއO0BGOXooA6GlA6G7RDXoGB~A6G(A lA6G3ol|~iA67GO0BR0R0GXouOXoA67GO0Bb0J0GXouOXoGL@BPJ IMlN4`A6G>?| 0`P2P7PQ0D%`P2P7F C/G0B0DXDݷOuXoC AP7_o H&BP0P} +L(:+KNF`4FFMb+2+G`JPQA7A6FF7AB7D OJlOoD0JOO_oD%B}C`O_o$#< C<FFBR7F`D0P_o77J7=???????FzBѶjn+FuBѶeXoFoB`A6Fh CBVt '(A8BqiXo7`7P`WR7B~`_ou`*'ub)2)3Kˋ;7 C0 C0PQ0PG`0PQ`0P`l C0 C07C`HCPQPQGu`7PEu`7AH.Dx@Interactive Read Error Dj @Trace memory @Overview memory, flags pN' D '4' Cdd  '8B(C'' C3A0@ Reference = I`Threshold circuit calibration+ 0 V Zero level - 4.267 V Negative limit + 4.233 V Positive limit - 3.333 V +10V threshold + 3.333 V -10V threshold + 433 mV ECL (-1.3V) - 467 mV TTL (+1.4V) `O` j72**Bl*" 76'$K**7 C2( C2'/߈?ӀP7рG7 'B2(Z'A67GB2)2+LB0GM'DNB0HMK2*;l" OB* A5;PBϕlϓQ ( )(u}HlHAA6GA<{'7}7yC7x7vAF#G}OqO_kl_ioA#GqA7aoA67GjS'^' A7PAMH'S'4AA6GODA7:B7tOsGHA#G=k,+G8oA67`G3DЇB'3ˀ3' 'Q Al*A6C7JG'R7B7=O Bm89 %lP?%3 A5>=P52%05 )S5E540%253--l +%,5.-5*5l'P5$H55 A5` Bl"l  C5%a5 C54l  C5H%T4P4Fll4ooo %Fl]Bll T4l745 C02 A0=qpqh|~ A4$ %( A4E4P4$ A4$ A4 A5  A4` Bl l  C44 C44l  C4H4P4ll4oLo UA $l$ $} A4l $4~$4sl $H4t$P4h A4kb4^oB4 C4 HlP $Rl NT0$KI C4G$ A4I\$? $ A4YXE4WS$U A4TP$Q A4QKKl L C4J4-H C4F4$l A C4?H4!;P4Bllllo4  $mlnoo|nB99jjr~~ 04C ?"0$&&0"l "mn "!"o <H7C98; =(6*:,D //,,14b&b0bLcT.Ud.VefWgXYuh[_i`2hZkpxsfI}UI˟џ˟㟬˟џ˟џןݟ韌˟Y韬˟kp}Ufş ---ETC--- all_boardsappendcomment configuration default display end exclude include listmessage preprocessorprinter repeatrun test_IMB_with stoptest till_fail all_boardP config_ preproc test_IMB stop #7L KMahCommand is complete to cursor positionSlot number containing included board Slot number containing excluded board Slot number containing AIMB stimulus boardTest to run on board in selected slot Listing fileCharacters delimited by ^ ' or "y           = Vuu -ˀA@33-CA >BV3Al #4@Bl DlFl"Gl'Il-Kl)Bt= .A<,<,F 2Ae C0qX! @yhuyqyiXoGB FDClAfECAcOB Gfaceigeneral pobes rHCBPC HPjuser interface 00hCUSER00HPuser interface 01hCUSER01HPuser interface 02hCUSER02HPuser interface 03hCUSER03HPuser interface 04hCUSER04HPuser interface 05hCUSER05HPuser interface 06hCUSER06HPuser interface 07hCUSqAW53iSyntax errorD333AAXA@;r4ƂY3wZ33x33A34@[ A x;X=uA>l(AvGiuOloDoB4'A4&33[A3\B433A7"[,uB2,3A=t,x]Z3x3XoW֢.e>C`~*)+'[Q58@7u=7tBl@lAbx^B77_b4)52,HMFcdx^YulS4R4Q44_`a ueflgZ7w;;xB7;7=cSelected test number unavailableuSelected board or preprocessor not in included list Board not in excluded listNo control board in included list No preprocessor attached to control board Board not in included list Board not in IMB list File not found for IMB boardML Disc number 0 to 7 only Comment maximum 80 characters xZlh 8Gh0u B hhD6dW5; " 0BG;h;DLih&jxZl Lt; RG69h D39_tXG6i6xZlh 8 h0u BGhhl6QoA;D 6xZl LupYGaCquuqloovvInpP (nterface16008:"lation bushC16008 HPC16008_E HP16032 interface16032 emulation bushC16032 HPC16032_E HP32032 interface32032 emulation bushC32032 HPC32032_E HP32132 interface32132 emulation bushC32132 HPC32132_E HP9450 interface 9450 emulation bus HC9450HPhC9450_EHPR9 pv_prepF0:HP :0001H ,  pTEST077P68Kl 66 æЦ ׬l NyHvJ_Yr4rFv,óv_ '6?IJM^vvvvvvvvvvvState Control and Clock64621A STATE-CT "(/9APb Mainframe interface and stimulus Control IC - shift registerClock IC - shift register Sequencer State count Trace memory Other counter testsIntermodule BusStrobe generator calibration #Preproc interface data bus stimulusRear panel PORT stimulus A6PP`@`?hC awxyzw{|BC}B~xz€w;3K;l" PB܂; A5˲;{FGIJUUD‚w{ƒJD/„ƒD,C…DD~}D"~}D~}AB~Ct#tq0"|@ APl oB‡̷XoqDPF‚wDN Ml]A;W UDU UDA O00;K|3 #3R33l[lR3Hu A3t0lBDPlA …[l[oR3HoB`AP0? MIDH?B3L3GlE†D[oD L3GlE†[o`P3A@ Register data =@All 0's 7@All 1's 1@Patterns@ Shift control @)NOTE: This tests only the shift register.  HkHnP` ̠Hn`H` Hn@ Not- HHkp@ Load ModeEPE‚D xˆ{#t@ƒtD†wA;w@ BDA CDB H00;KR3 #3J33l[lJ3Hu A3t0lBÇEPE0JPE …[l[oJ3Hoة79;=?UWUUEA}0@Register input bits `Di@10Dj@All 0's H@All 1's @Patterns@External Clocks HkHn@ , not blocked ̐IJKLMNpQPT@@/@?@` $@/@@/@ @ @K‚wx[DD>DE m+}B‡E~B†B33Ew JB…EK[o‰]B3R3Š‡u񃷖XoE] (CG(FJC…K[oŠ}A~EKNJCw~DDDQDBBDŠ~3AEPHDEA[o~3AEEFD{BEAHD{E2[o~3BE6FDlE'[o~3BE+HDeE[owAE#‹‡ˆz@EtD[„DuDVŒ}A}BDRBDlEG…[[oR3DDDl',F…[[oE[oJ3'3BD/-0qpBBDlG…[[o'A@t%0DD}Dl DtlDuDEa3R3w~ˆ„DCDzDD w[{D0DlJ0D`P`H@3w~‡vXo€{‡zDylI†DzuI†Ko<33w~ˆzLD`uD$DcuD!w F3~KˆzLDO3K˃uoKlD[˃Kl DBu6JClGD:u9I y$A5;mB5@=DB?BDB99`PGP˶,*G`PQB B#%`P PGAuE@uo"}<θ CoA﫛 $ ̾ `@Reset Hn`P ̐ `@ No carry@ Inc @ Load @ Early carry p4 ̐\ ̐ ̀HnHk ONHnHkP Di@54321_98HqDjQ@State Register Count_@Load@Occur Counter Bits True c@False K@RAM Hb@MemoryHb,@ , Trace Point @SequenceHb@ing Y@ Functions h#@(HSTR,LSTE,LSSE,LSME)  Address hVM‚D DD=DYDe+BŽAﭙwDDDqDp`PQC…`DDG3ŒD„ŒD|„[oDYP0AE…B @A?FGDG08AqyDꅈBDZzMl0DUHGHGDGzkDHoDFL3˃uAD9zDK0L0QDKHADKoD*{„|BChqGPQ7nn7l3̓ˈJS3΃`DS…XQUY~^~]1l0l/+%V + C a c b /?/jHDiHvDjR@ Reset to 0*H@ Count enable@ 10/10 count@ 20 bit count@ Output test S@0's P@1's !!3)%@: ̠@ never enabled @CE input stuck high @always enabledh<HnHkP!!KKK[[3IpPSTC aW`H` @/O‚xD D@DiDDD+BDEC†ED†EE†DD JC…D JD…DE…„K[oDC…DD…DJE…~zDDDJC…DD…DEJEDD$zAD ‡{3D„[oB3D3|B JP JF…K[o‡ztw }A~{x3w€zw€„[oG3iB3;DzDK[o|C J3 … J3 (C{zI3HAo{„B3C3w€zK 3̃3l w€zoL3D;A3!0qploAl3B3;GcuK…K[ow ˆzD w~ˆzD„D"wlDvNw~B333B؆`P`PPEAŽA1X76 ` 4%>\AP?D8 ; Hn@: ̣HkH@ Never Set H@ Set Early pP ̾ `@Reset Hn`P % HDiH@Bit Dj#Di @Memory Channel DjPHq$@1098HqHvHHPH@ RegPH@, WrapP@Store seq state V@ mostly 1'sP@ mostly 0'sJH@Test@Index HAddress CounterMeaP Osurement Complete Trace PointI‚w‘’“DDQD+B-3D3B3K˃A”’D•DtDK“AllKˊB[Kc3[oK̋…oKz9VV@AU U ”˜zC™šq„t@„q“4444D̰444 EAF…l44|4yr rDwAF…›]Gœš”BqNPt@Kq“4_4\B4\Df4Yc4V`4SL LDQAF…lT4JQ4GN4D= =DBAF…›.G’›‘”z˜zC™šqzCD0 It@0XozCq“HO)yH*4 UVUVUVUVUVUV UVUVUVA6F0BD)0P÷@?R8D  EPI7t w P 'J7'}D/0(/DBwl>wXo7?E8B8B (C(C8OOXo7?}E00wHXo_oH@1 @2 @3 @ Time enable @ Time resetH@4 ŽA HnHk Prescale TCC?@ ?4?`aaa aJ‚B3EwxDDl)D D wˆDlA6wˆDDKBlC3„D{ C †{qB3Db3DDKKы|9F…DwˆDBCPQD[DzLwˆzLDJwˆD zKDA„DDBD?zDBD;tDBD5wˆjDzLDDAPD'{_D zKDDAPD„DDBPDlNDqDDAPlPrGB5`PQ& '(E33l %''BD*D'D&D%;B3%'PQDP`DPPADP`PD '(HҰ '(IӰc3A0PEE(@``@?B333΃u7wˆ„ G`3KKo`cCJ JPQc3&%&&A6&;%&&.A63DCBA6&B%&&DˏJ `PDi@Internal testsDjU@Master[@Trigger U@Storage OKDi@Tests with IMB test board Dj`#HU@Receive 9@Drive :Di@IMB test board limitationsDj`"@(1 = Not tested)U@Drive @Receive @ Enable P`@( H:P`@(Port1 pulses,PDC,Port2,Port1,H:A$QP#"U HC@ in slot "DjG ̐L Hk`#PHn@: ̡ H1@True H1@False  Function never LME,LTE,LSE,HTR)  No IMB test board w‰]nxˆCBt~pOx`x`x`x`x`x`x`x`XV@11 uSec between strobes Ꞑ,``BO' A003qxq`|~C;|~A3Aﴟ@ Read address: P@!Write address 0 with walking ones !@: ! !@: ! PB33KCw{~Bx3D3qˆzDŒ[o3[oq@LPORTS 1 & 2 and clock cable strobes are driven with Triggers and Trace Point9AGMRX^j}ysHҶSƙ4IB0?xxxx40 Channel Acquisition 64622A STATE-40 AW`ihw~Q‚BŸIŸO ¡B¢BuD¡B¢Au PA A Aﵧ @Banks cannot be seperated `@Banks cannot be combinedpPHkpPDi@Bank A.Dj2Di=@Bank BODjP2DiHqDjH𐠈=@ RAM Adrs: @Bank independence: XA*hhŒ[‚BA£NA£W3B33‡OPCI¤8BB;B‡OٷB¤8ÈBBcҰb)2)AEXAElAﵧDi@Bank A(Di7@Bank BODjhXAsAZAZ@Bank Independence:OA¥DD DDD+BB3QClBFlM¦CCF3§u3JIªNŽAﶬX XAﻮH') XAA'`@ Data Channel`DjP;HvꞐ* ". c3""y7H*Zƽ ·4AX}²[ '0;COX20 Channel Acquisition 64623A STATE-20 AW`ip{+Interaction with control board and stimulusResource PatternsSequence Patterns Trace memory Overview event memoryOverview/Range decode RAMs Overview/Range functions State countOther counter testshhhhh hhpK`w«¬OB­t~At}~zw{R3PPQDR300G3BHH[o[o[ow{OƷphR QhD‚w®00{ƒJD3OBPƒD-OC…P3`0۰BH[o(3D DB Cooq"|@ CPloqBA8 HkHn @Strobe Request@Release data busxhhpw~I‚B3O }DDl D(¯Bl"D&¯ClB3B3DD3¯DD¢uD D3K :t0K =t*D++D=BlD:=lD6B00=4.- Gl3tHL%oD##0$03qyt~3 8θHt| &8J4 (IH\oOBA     P P *HkHnM@Resource Pattern: DiHqDj H8H}@true3H}@false +@Data bits: 0 to 3@ RAM Adrs: @ 4 to 7@ 8 to 11@12 to 15 @16 to 19PPP All patterns hhhpIKQŒN‚BBl3;~BF3'3;DyDQB3'3;DolllB }@oKGlo D[DBDk‡DsOBDwEDc }@o AoA33CID)(ABPBD!B3B;D4PE$GPQDBEDK loKK =)  0‡D3D8D E+++PBxvxPIJCl‡u;°G`PQjOBcPQuB`XoGu>DGۀBAOuTlQKOOGAEX P ̈! ̐PW@Sequence RAMs:@Address @PatternsPDiHqDj Di@3210Dj2H}@true,H}@false %$@Data bits: 0 to 3@ 4 to 7@ 8 to 11@12 to 15 @16 to 19PP hLBD DDDD=D^+B;‚w~B3QClBElJDCCE3Dju33K`DbK t:3;DOD3`D[oB3 ;HG3?D@DDK[oD:DD?u APQ'…K[oD3KDKA3DDq„Œ~€DkzGŒ~€„CD7KHDgu{B3G3C33PQ3$/3 }33±C |²DcD  JP3 (D…Cc J3 … J3 &(Cꅻz""33DDUUffwwPQ A R3DŒuz€OB`@@?ŽAﻦX   '%  HkHnHDiH@Bit Dj&Di`@ Data Channel`DjPHq'Hv+HSR@zeroes$H@onesH@testH@ counter reset @Store Qualification Address Data all hhphhx `P0?I‚Š-OʷBDDD+DBDelx~2D C…~1DCJCDBlDB3u@ #BXoD JD…BCoDDBD D D|DDwʷDDuJEBtD D QDBDʷQDPDODMDIDCl3DQDMlQJu.QB`PQFBD CDDDFDJDQ3D9D5BDD JGDDQ33D)bͿ[t~D$Q3B3D-JuH…KoBQ0 CPQBC3˷7{O5J0Pu`CB…P`P'&G`GPQAｉDi@10Dj@- valid data flagsg@Interactive readP_Di@MW1098HqDj@- meas. complete, wrap, address @@ Store enable8@Address counter .@ Wrap controlP(Di@3210Dj@ - data bits @ Null detect @ Data path @RAM testPP ̐  ̐P hhxh hpOPO@DVwxDOwO+BODDzO~l ~O³O³O{„O׷÷ŷt{D t|Dt~÷73A3B33KuI‚«¸¹DD:Dfo 3C3·¬DODDDDKԃt3¶»KK ldzKN ~ | ·º½¿ˆOqŠt@t@q¶»J3J3P3FD'¶»FD"º¶»Gl·¬z¿ˆOqŠD0 Kxt@0Xoq¶» HP?cu†ŽAH@1 @2 @3 @ Time enable @ Time resetH@4  HnHk Prescale Ꞑ(A6ľ S4ÇB4ķllĵÿlBlAlħÿAAl4z$4y C4ĘCÿlx$ A0 A0;4q`qhL||Pqh0PI`q`q`q`qhqhBqaCqiq`qaqa ~(C (CB ?(A,7Al(Rh;B45l -,)(JFE4+l D4(l I4%lH4"lG4DBy'^`p#A6 S4B4 :llUTl uLoLoE4lD4lI4l$0 J1 A03qxq`|~{Cpo(K<B~ĽCo (D8 O0qxq`qxq`(A8 N0qpqhqpqhĠCoAlęq~~ĒCo(K }(ĄCoHlo Kk(M}|f Lwb(JPt s4e Cp~`IltCi]{CpovVokulLo8(JPul$;B#|42{ C4-5CoL+PI$ A003qxq`|~!Co9B4 By`^pqrsA6 S4B4 :ēllđđŚŘŔŗluĆLoLoE4lD4y{lor$q4o n(PHz$b4cy C4^YŕCŚŘPW0(A8 Jl#8qxq`|~Bqa Kq`Cq`q` ~(C qa<;(Jd74*ll:qxq`|~Bq`q`q`q`Cqaq`wq`l p(Rl;BiI4odEy` $ A4 4B44ŬŪŬuz$b4cy C4^YŕCŚŘPW0(A8 Jl#8qxq`|~Bqa Kq`Cq`q` ~(C qa<;(Jd7ȔZũoAӛ1א\hjÚdǀK VZuEןFH\[]堹Gyd/[nPq랐&0F>82" N PR@B$<T6hi!񬱐4iJźH#Ƚ.LXD:HٽĽ;Cxнӽ־Dɨ N pPpP@ ADRS DEVICE eC74A "Ae|tiyh_*oAAA AA  ADAAPu>AD?(AAo@>@`DLSUIKEGHJYl^D9ET A6D} ؾ؃8/10 MHz State Controller 64621A STATE-CTAABBDEHIKLOL8 0BBBBѷA6 (CB|BC3|A6F0O3η|~XolR4A6DG\oB@?C aA6GGG}G|oCaؓ $$""&&ؤ?ث@BDFACEGA6GqDOPuPu7GzػlD%3D`PE7g7B7LJP@0PI`'7PB'7GOGjئGvثGNo]PQ'4GDGoGEGTCPE0gw Pt@v`lt@ vBlB7G$G?ئG%G4"Bece'-``@?TA6PE'FB77u7FG 1G6FFBPB`OOoAet segment to be overlayedNumber of entry to bD9EA)Z@`uHIgy^`pqrsbZd'0eђ>e<>m<йPT!~}\\ ] v!)1@lLeӁDk3ҕҕBӧʠVҖҖAӦB 8<@A,D:General Purpose Preprocessor 64650A L]l}ȑȦȵ!Clock / Data Channel VerificationControl / Status Verification!Interface Module I/O Verification'Rising Edge Setup and Hold Verification(Falling Edge Setup and Hold Verification Triggers, Trace Point output &Sequencer, Measurement Complete output 3Interface Module I/O Verification Failed: 0 7`bUUUU""``GEDBD~DEDA73FD(˷@t>A6cDHDE00ju;qx lqx`HXo;lD D3DoDoE0 }(A; j#րP˳ C0 jSPQBB3;lD oD o#4BCA3C333Di3B3D;DDBDDzCDK :2DrKERoO333DhC3B3`P3DDfBDpDRDaCDkDMK :-DMKGBo33PE$$ A|S3T3lS3T3PE#$ A|c3lc3UUeUZUZUUj@@`P3`P3AtGlGGc3"t@lAuGGGoGGGol&π AA3A҄C3llDAoDAʽo3&,3+P /@Pod "@: 7P ͈ @Pod "@: %K D3  0P0 DiHqDj/DiHqDjP@Clock Edges, Positive: &@ Negative: P@Clock Qualifiers, High: +@Low:```````````` @CBDCDEDGDHDIDJDDDD%B`÷D0D i( ; P(; @ Pass Hn`  b @ Pass Hn`  YX`  @ acq bd not present Al@l?B; '(X(C;T3DR@4 Addr 1 Addr 2 Addr 3 Addr 4 Addr 5 Addr 6DSP>@Latch Read/Write@ ECL Hi Value@| *@Clock 5 EnableP@Halt Request Circuitry@| *@Clock 4 EnableP@Interrupt Request Circuitry @| *@Clock 2 EnableP@Status Latch Control@| *@Clock 3 EnableP@Address Latch Control @| *@Control By Interrupt AckDR@19 -- Pod 1 Data -- 0 DUDR@19 -- Pod 2 Data -- 0 DU7DR@19 -- Pod 3 Data -- 0 DU)@CLK 7 @CLK 6 (@CLK 5 ;@CLK 4 P@CLK 3 @CLK 2 (@CLK 1 ;@CLK 0 ' DC' D$,4'4' '0P0PE$|T4T4lT4T 4ma""dDDUUiUZUZUUPh' C%!4DGBM5\]ZlW2* **}8 **o' C$GlJ5A '(CBGl '(CCGl ' CPI]/oBHAҾ'5! C,݈=,܈=ADGGD=' CGnt@䇙PtAҰA҄XC5)+5)G' j5%Gll 5 DA" o5D A  oA+$4BC4 4ҢBGrGtll2Uo@`DLSUIKEGHJYl^clock, TTL threshold @WARNING - NO CLOCKS pPock, TTL threshold @WARNING - NO CLOCKS pPC``ZY%*&&t8^̖̕ țțțʖțț GP ProbesClock: 64636A, Data: 64635A=MbxȇClock/Data channel verification)Set up and hold verification, rising edge*Set up and hold verification, falling edge Triggers, Trace Point output &Sequencer, Measurement Complete output Ȟ""`GDDLDo0RqpXo)uABD#D 00jqx`HXoEElD D3DoDoD CPQB;EElD oD o#4BCA3C333D3B3D;DDBDDzCDK :2DrKEo333DhC3B3`P3DDfBDpDRDaCDkDMK :-DMKGBo33PE$$ A|S3T3lS3T3PE#$ A|c3lc3UUɸUZUZUUɽ@@`P3`P3AtGlGGc3"t@lAuGGGoGGGol' A63AC3DDllDAoDAo3&3+P /@Pod "@: 7P ͈ @Pod "@: %1K D3%̈<@Recommendation: @Unhook Probe Leads  0P0 DiHqDj/DiHqDjP@Clock Edges, Positive: &@ Negative: P@Clock Qualifiers, High: +@Low:' DC' D$,4'4' '0P0PE$|T4T4lT4T 4ʽ""DDUUUZUZUUPh' C%!4DGBM5\]ZlW2* **}8 **o' C$GlJ5A '(CBGl '(CCGl ' CPI]/oBHA'5! C,݈=,܈=AˠGGD=' CGnt@ׇPtA AXC5)+5)G' j5%Gll 5 DA~ho5D A|hoAy+$4BC4 4BGrGtll2UoPH#H'PH#H'P H#H'PH#H'P HC?Dq3S3[oqA̶0rmnC3@:Measure delay from rising edge of any clock, TTL threshold @WARNING - NO CLOCKS pPCGq3nS3[oqA̶0@:Measure delay from rising edge of any clock, TTL thresholdCGCt@t@t@3qA̶X@!Connect clock input to BNC PORT 1 R@%PORT 1 is driven with sequence events pPCGq3nS3[oqA̶0@:Measure delay from rising edge of any clock, TTL thr 0fR&DN.,$ 28*(2KF *(@o@>@`DLSUIKEGHJYl^D9EA)Z@`uHIgy^`pqrsbZd[\^ ]_^` _a`b acbd cedf egfh gihj ikjl kmln monp oqpr qsrt sutv uwvx wyxz y{z| {}|~ }~    ! ! " "